一块基板不再通吃：先进封装基板为何走向应用专用化 —— Semiconductor Engineering 精读

来源：Semiconductor Engineering（semiengineering.com），栏目 Systems & Design，作者 Gregory Haley，2026 年 9 月 28 日。 原文：One Substrate No Longer Rules Them All — https://semiengineering.com/one-substrate-no-longer-rules-them-all/ 体例：编辑综述，汇集 Prismark、Intel Foundry、Shinko Electric、Amkor、Brewer Science、Applied Materials、Lam Research、Synopsys、Mitsubishi Chemical Group 共九方陈述。原文正文无配图。 转载说明：第一部分为英文原文完整转载，版权归 Semiconductor Engineering 所有；本站仅调整排版与标题层级，不改动任何文字表述。第二部分为本站独立撰写的中文结构化解读，其中的质疑与推算属解读者观点，不构成投资建议。

第一部分：英文原文（Original Article）

Key Takeaways

• Larger body sizes, higher layer counts, finer routing, and embedded functions are increasingly making substrate capability application-specific.

• A substrate can be technically feasible but impractical at the yield or process window required for high-volume manufacturing.

• As substrates specialize, the carrier systems, temporary bonding materials, and many process flows around them must specialize, as well.

---

For years, the substrate problem was relatively easy to describe, even when it was difficult to solve. Make enough of them, at the required dimensions and yield, and advanced packaging lines can keep moving.

The shortages that put ABF substrates on executive dashboards reinforced that view, and capacity remains a big part of the overall equation. But a supplier can have available capacity and still be unable to build the substrate needed for a modern advanced package. Larger bodies, more layers, finer routing, new dielectrics, embedded components, and tighter mechanical tolerances often arrive together, turning a supply problem into a capability problem.

Economics are beginning to expose the shift. More money is being spent on substrates without a proportional increase in the number of substrates shipped, because each one requires more material and more structure. In AI and server packages, that generally means larger areas, additional layers, and more demanding interconnect requirements.

“Substrate value is rising faster than shipment volume because packages are using higher layer counts and larger body sizes, which increase material consumption,” said Yu-Po Wang, principal consultant at Prismark, in a recent conference presentation. “The strongest growth area is still servers, particularly large-body flip-chip BGA packages.”

Capacity for what?

The old capacity question now has a qualifier attached to it — capacity for what? Even if two suppliers make organic substrates for roughly the same package footprint, they might not be interchangeable. Each package architecture imposes its own acceptable combination of materials, dimensions, and process limits, so matching the footprint is just the beginning. Dielectric properties, line and space, layer stack, CTE, embedded passives, power delivery, thermal behavior, and the assembly flow can significantly narrow material choices. That narrowing begins with the growing amount of system functionality being pushed into the package itself.

Chiplets help address part of the silicon-scaling problem by allowing large systems to be divided into smaller dies and combined later. But the functions that once lived together on a single piece of silicon still need to communicate after they’re separated. Signals have to cross the package, power has to reach each die without excessive loss or noise, and HBM has to sit close enough to logic to realize bandwidth benefits.

“From the package point of view, the package is not just a protector. It’s actually carrying quite a bit of signal and power,” said Tarek Ibrahim, senior principal engineer at Intel Foundry, in a recent presentation. “So we optimize the dielectric and the design rule working with our vendors, equipment suppliers, as well as our substrate suppliers.”

Those additions turn what used to look like packaging choices into system decisions. A dielectric is selected based on the influence of its electrical properties on signal propagation, not because it survives lamination and assembly. Layer count affects routing capacity and power delivery. Embedded passives can shorten electrical paths but consume area and add process steps, while optical integration brings its own geometries, materials, and thermal sensitivities. The substrate is still underneath the dies, but it is increasingly doing work that determines how well the dies function together.

The specialization happens within substrate families, as well as between them. Organic substrates are no longer broadly interchangeable when different packages require different core structures, layer counts, and embedded functions.

“We have three types of core-layer structures and four-, six- and eight-layer cores,” said Yasushi Araki, corporate officer and general manager of R&D at Shinko Electric, in a recent conference presentation. “Now customers are asking us to embed passive components in the core for power integrity.”

This makes the familiar organic-versus-silicon-versus-glass debate somewhat misleading. Those remain important architectural choices, but specialization is already occurring inside each category. That specialization becomes more consequential when the design has to be manufactured repeatedly rather than demonstrated once. A layout tool can draw a finer line, and a package architect can ask for another build-up layer, but neither decision proves that a supplier can make millions of those substrates at an acceptable yield.

Yield makes the real design rules

The boundary between what can be designed and what can be manufactured shows up when customer architecture, OSAT assembly rules and substrate supplier process limits have to coexist. With new advanced packaging dimensions, the design rule has to survive more than one manufacturing window. A geometry that works for the package architecture still has to be something the substrate supplier can yield and the OSAT can assemble reliably.

“We may want certain design rules, but the substrate supplier may tell us that if we do that, it will hit their yield because these are large-body, multilayer structures,” said Joe Roybal, senior vice president and general manager of the Mainstream Business Unit at Amkor. “We need to make sure the yield is reasonable, and at some point we also have to adapt our assembly process, whether that is standard mass reflow, laser-assisted bonding or thermocompression bonding.”

A specification therefore can remain technically achievable while becoming economically unattractive. More layers introduce more chances for defects and registration errors. Larger body sizes give dimensional and mechanical variation more distance over which to accumulate, while tighter routing reduces process margin. The difficulty is rarely one spectacular failure mechanism, though. More often, it is the narrowing of several tolerances at once until a substrate supplier’s nominal capability no longer translates cleanly into production yield. The loss of repeatability across designs may be just as important.

“These days, we don’t get to say, ‘Oh, we’ve done this one before,’” added Roybal. “Each customer is different, and there is development work we need to do before we’re ready for verification and high-volume manufacturing.”

Body size, die placement, pitch, and thermal constraints can differ enough that an established process window becomes a starting point rather than a reusable answer. That changes what “second source” means, as well.

A supplier with unused factory capacity still must reproduce the required stack, dimensions, electrical behavior, and process yield before it becomes an interchangeable source. As the substrate becomes more specific to the architecture, the qualified supply base can become much smaller than the nominal supply base, and that specialization begins to propagate into materials that are not part of the finished substrate at all.

The stack changes the material

A substrate does not travel through assembly untouched. Depending on the flow, it may be attached temporarily to a carrier, heated and cooled repeatedly, coated with dielectric, exposed to plasma or wet chemistry, plated, thinned, debonded, and cleaned. Each operation renders the next one a physical structure with a history, including residual stress, warpage, surface condition, and materials that have already seen several chemical and temperature excursions.

Temporary bonding materials sit in the middle of that history. They may come into contact with polymers, dielectrics, metals, silicon or glass, and they need to hold increasingly thin structures securely through processing without becoming so stiff that they introduce additional mechanical stress. Those requirements can change with the surfaces involved, the thermal budget, and the amount of warpage the material has to accommodate.

“The design of these materials should be very application specific,” said Hamed Derami, advanced semiconductor packaging materials manager at Brewer Science. “One temporary bond material might work for a specific process and not another. We usually redesign the material around what it will come into contact with and the adhesion requirements of that process.”

That process window can be narrow. Too little adhesion and the package can delaminate during processing. Too high a modulus and the temporary-bond layer can add stress instead of buffering it. Total thickness variation also matters when fine-pitch RDL is built over the bonded structure, because local thickness variation can degrade RDL uniformity and resolution across the wafer. As a result, Brewer tunes the material around adhesion, thermal budget, warpage, and the other requirements of a particular process flow, rather than assuming one chemistry will work across different architectures.

That change doesn’t always require a new package architecture. A different mold compound can alter adhesion and mechanical loading, while changes in cure conditions or thermal budget can affect polymer behavior. “Even if they go from version one of their packaging to version two, we might need to change our material,” added Derami.

Moving from wafer to panel adds another set of demands. Non-uniform coatings, along with higher stress and warpage, can require temporary-bond materials with greater thermal and mechanical stability for panel-level packaging.

Glass shows the same dependency inside the permanent substrate. A copper-filled through-glass via expands and contracts differently from the surrounding glass as the structure heats and cools because the materials have different CTEs. Applied Materials found that lowering the CTE of the liner between them was not sufficient by itself. If the liner modulus remained too high, it could not deform enough to absorb the strain, while a low-CTE, low-modulus liner reduced cracking by addressing both the thermal mismatch and the mechanical response.

“There are a lot of questions around the idea that changing the glass material changes the process,” said Poulomi Mukherjee, process integration engineer for advanced packaging at Applied Materials, in a recent conference presentation. “That led us to understand that we need to have a solution that works for different types of glass so that the downstream processes don’t change.”

The objective is process portability, but the need to engineer that portability exposes the underlying problem. “Glass” is not one set of mechanical and interfacial conditions. Change the composition or properties enough and stress, seed adhesion, and downstream thermal behavior can change with it.

“All these process steps have their own challenges,” Mukherjee said. “They have to work individually, as well as work in a co-optimized way together, so that the upstream and downstream processes do not interfere with each other.”

By this point, substrate specialization has escaped the substrate factory. The carrier can change, the adhesive can change, the liner can change, and the acceptable process window can change. The next constraint lands on the equipment expected to process all of those variations.

Equipment must evolve

After substrate choices alter materials, stress, handling, and process sequence, equipment makers inherit the variation. A tool that was designed around a familiar wafer thickness, dielectric system, or via process may have to operate across larger panels, more build-up layers, and tighter line-and-space requirements — all while maintaining uniformity over a much larger area. That creates its own development problem for equipment suppliers as larger substrates, tighter routing requirements, and multiple emerging process options push tools beyond familiar process windows.

“The industry has not yet converged on what the real paradigm will be, and all of these approaches require a lot more investment and development from the equipment industry,” said Prahalad Parthangal, technical director of advanced packaging at Lam Research, in a recent conference presentation. “We need to understand how we standardize and how we develop something that is fully capable of sustaining the industry.”

Until that convergence happens, equipment suppliers may have to support several competing substrate approaches without knowing which one(s) ultimately will reach high-volume manufacturing.

This creates an awkward capital-equipment problem. The equipment has to be developed early enough to enable a substrate technology, but the technology may still be competing with several alternatives. A glass-core flow may need different handling and via processing than an organic build-up substrate. Panel processing introduces its own deposition and uniformity requirements, while finer routing can push back-end processes toward techniques that look increasingly like front-end manufacturing. Supporting specialization therefore means designing and purchasing equipment before the eventual production mix is fully known.

That uncertainty is easier to justify when one application dominates the roadmap. However, the substrate market is heading in the opposite direction with AI, optics, automotive, and power packages pulling design requirements toward different endpoints.

The best choice depends on what the package has to do

AI and HPC are currently pushing some of the most aggressive substrate requirements. Large logic complexes surrounded by HBM need dense routing, many layers, high-speed signaling, and increasingly difficult power delivery, while the package itself grows in both area and value. Those requirements favor technologies that can support large body sizes and high wiring density, but they do not establish a universal architecture for everything else.

Co-packaged optics is already exposing how quickly the hierarchy can change. The electronics, photonic ICs, optical engines, fiber attachment, and thermal solution have to coexist inside one package, and the manufacturing infrastructure is still developing around several competing implementations.

“One of the challenges here is because it’s so new and everybody is kind of trying to blaze their own trail,” said Suresh Jayaraman, senior director of package development at Amkor. “Each solution is kind of unique, and everybody’s building custom solutions. If we invest and say, okay, we’re going to support this particular architecture, it may or may not port over to someone else.”

The differences reach directly into assembly. Some CPO approaches can reuse elements of an existing 2.5D platform, but optical components do not behave like ordinary dies. Attaching them can require equipment that was not previously part of the OSAT toolbox, while small amounts of contamination that might be tolerable in an electronic package can attenuate light around micro-lens arrays. Manufacturers consequently have to consider new attachment, cleaning, and inspection capabilities for those optical structures.

Even the material immediately around the optical path can vary by architecture. Some architectures use an index-matching epoxy to attach the lens to the interposer, while others require a clean air cavity instead. A substrate or interposer optimized for conventional electronic routing may remain useful as a starting platform, but the optical architecture can force enough changes around it that the manufacturing flow becomes application-specific.

Automotive demonstrates the opposite pressure. It is adopting more advanced packaging for ADAS and centralized compute, but much of the market continues to rely on mature package types because qualification history, cost, and long-term reliability carry different weight than they do in a leading-edge AI accelerator.

“Although we’re seeing significant growth in advanced packages, the workhorse of automotive packaging still remains traditional wire-bond packages,” said Prasad Dhond, vice president of BGA and QFN products at Amkor. “We’re using material sets driven by lower cost and higher reliability, along with automotive-specific design features such as wettable flanks that improve inspectability.”

That contrast is important because specialization doesn’t always mean moving to the most advanced substrate available. An AI processor might accept additional layers, expensive materials, and aggressive integration to gain bandwidth. Many automotive applications still favor mature architectures with long reliability histories. High-voltage power devices emphasize thermal paths, isolation, and materials capable of surviving very different electrical stresses, while CPO adds optical cleanliness and alignment constraints. The substrate hierarchy changes because the optimization target changes.

More suppliers do not necessarily mean more supply

The divergence has a supply-chain consequence that can be easy to miss when capacity is discussed in aggregate. A substrate supplier may have open production capacity, but qualification depends on whether it can reproduce a particular layer stack, material system, dimensions, and the yield needed for the design. As those combinations become more specialized, switching suppliers becomes less like buying an equivalent part and more like qualifying another manufacturing process.

The stakes rise quickly when the substrate sits beneath expensive logic and memory. Intel Foundry is working with partners to bring more silicon-like yield infrastructure into substrate manufacturing as package size and the amount of embedded silicon increase.

“At the end of the day, I’m trying to maintain a known good substrate, so when I attach the silicon, I’m avoiding any loss due to the substrate being not functional,” said Intel’s Ibrahim.

That changes the economics of substrate quality. A defect in a relatively inexpensive substrate is one problem before assembly, and a much more expensive problem after high-value logic and HBM have been attached. As package cost rises, inspection, process control, and substrate qualification have to move upstream because the package can no longer afford to discover substrate failure at the end.

The same logic makes second sourcing more difficult. A nominally compatible supplier has to demonstrate that it can meet the specifications, and do so repeatedly enough to protect everything subsequently assembled on top of it. Capacity remains important, but useful capacity is the portion that has been qualified for that particular architecture.

Design files have to become more specific, too

Physical specialization creates a less visible problem upstream. Engineers can’t optimize a substrate as part of the electrical, thermal, and mechanical system if the design environment knows only its outline, routing rules and a few nominal material properties. That becomes particularly difficult when the substrate, RDL, interposer and assembly process come from different suppliers.

“There is still a lot of opaqueness around standardized information for package substrates, RDLs and interposers,” said Amlendu Shekhar Choubey, senior director of product management for the 3DIC Compiler platform at Synopsys. “Material technology files for thermal and power behavior for interposers and substrates, in a format that can be integrated into the design flow, are still lacking.”

Thermal behavior belongs to the complete stack, not any one component. The die, mold, interposer, substrate, and even the PCB beneath the package influence the result. Leaving those pieces out can make the thermal analysis wrong. As substrate architectures become more specialized, their digital descriptions need to capture more of that electrical, thermal, and mechanical behavior, as well.

That is difficult in an ecosystem built around proprietary processes. Suppliers need to expose enough information for system-level analysis without revealing the manufacturing details that differentiate them. Bhatt described materials suppliers, equipment makers, and fabs as separate “black boxes” that increasingly need to exchange enough information to iterate together.

“There isn’t going to be one solution that fits all. Every process is going to require some customization,” said Sanjiv Bhatt, senior director of marketing and business development at Mitsubishi Chemical Group. “For that customization, one person cannot do it all. You have to have collaboration that allows you to move forward.”

Until that design and data infrastructure matures, some substrate decisions will continue to depend on incomplete models followed by physical test vehicles and qualification.

Conclusion: No single successor

The temptation is to turn every substrate discussion into a succession story. Organic substrates dominated one generation, silicon interposers enabled another, and glass or panel-level technologies are positioned as the next replacement. The actual development path is becoming messier because each solution removes a constraint while introducing another.

Glass can provide dimensional stability and support large formats, but it brings new TGV, adhesion, handling, chipping, and cracking problems. Organic substrates retain mature infrastructure and cost advantages, while finer routing, additional layers, and embedded functions continue to challenge what they can do. Bridges and fan-out approaches can reduce dependence on large silicon interposers, but they bring their own process-control and yield issues. And none of those choices optimizes power, bandwidth, thermal behavior, reliability, cost, and manufacturability for every application at once.

The more consequential shift is that substrate selection is moving closer to the beginning of system architecture. Package designers increasingly have to decide what the substrate must carry, how fine the wiring needs to be, what materials can survive the process, what the supplier can yield, and how all of that will be modeled and qualified before the package is locked down.

As heterogeneous integration pulls more of the electrical, mechanical, and even optical system into the package, the substrate underneath it becomes harder to separate from the architecture it supports. The industry is no longer converging on one substrate to rule them all. It is learning how many different substrates it is soon going to need.

第二部分：中文结构化解读

零、速览

项目	内容
来源	Semiconductor Engineering（semiengineering.com）
栏目	Systems & Design
作者	Gregory Haley
原文标题	One Substrate No Longer Rules Them All
发布	2026 年 9 月 28 日
原文链接	https://semiengineering.com/one-substrate-no-longer-rules-them-all/
体裁	编辑综述（汇集 Prismark、Intel Foundry、Shinko Electric、Amkor、Brewer Science、Applied Materials、Lam Research、Synopsys、Mitsubishi Chemical Group 九方陈述）
一句话主题	基板的能力正在从「一种板子满足所有封装」走向应用专用化，而专用化会把材料、载具、工艺窗口、设备与设计数据基础设施一起拖进不确定性

一、文章的骨架

这是一篇结构极清晰的「连锁反应」文章，四层依次传导：

1. 问题被重新定义。 过去基板是产能问题（做够数量就行），现在它先是一个能力问题——供应商可以有闲置产能，却做不出某个先进封装所需要的基板。价值增长快于出货量增长，因为每一片都要用更多材料、更多结构。
2. 「产能」必须先加限定语。 即使两家供应商为大致相同的封装尺寸做有机基板，也未必可互换：介电特性、线宽线距、层叠、CTE、内嵌被动件、供电、热行为、组装流程，共同把材料选择收窄。专业化同时发生在分类之间（有机 / 硅 / 玻璃）与分类内部（core 结构、层数）。
3. 良率才是真正的设计规则。 客户的架构、OSAT 的组装规则、基板厂的工艺极限三者必须共存；几何上可行不等于能良率量产、也不等于 OSAT 能可靠组装。结果是「第二供应源」的含义变了——不再是买一个等效零件，而是再认证一套工艺。
4. 专用化溢出到材料与设备。 临时键合材料要按接触面与附着需求重新设计；玻璃的难点不在玻璃本身，而在玻璃与铜之间的界面（liner 的 CTE 与模量）；随后设备商继承全部变异性，且必须在工艺路线收敛之前就投入开发——这是全文唯一的资本支出风险。
5. 下游还有一层：设计数据。 基板/RDL/interposer 的标准化信息仍然不透明，可用于设计流程的热与功耗材料技术文件仍然缺失，材料商、设备商、晶圆厂是三个互相交换信息的黑盒。

二、核心机制拆解

主张	原文给出的证据	我的判断
基板问题已从「产能」变成「能力」	价值增长快于出货量（Prismark 的 Yu-Po Wang）；层数与大 body 提升材料消耗；最强增长是服务器的大 body FCBGA	成立且有清晰的财务含义：涨价来自「每片更贵」而不是「更多片」，因此基板厂的收入弹性主要靠结构升级而非放量。
同样的封装尺寸不等于可互换	介电特性、线宽线距、层叠、CTE、内嵌被动件、供电、热行为、组装流程共同收窄选择	成立。这条推翻了行业里一个习惯：按面积/层数比价。真正可比的是「材料体系 + 层叠签名 + 工艺窗口」的组合。
良率是真正的设计规则	Amkor 的 Joe Roybal：想要的设计规则可能撞上基板厂良率；还必须适配组装工艺（mass reflow / 激光辅助键合 / TCB）	成立，且这条是全文最可操作的判断。它把「设计规则」从几何约束升级为「跨三家（客户 / 基板厂 / OSAT）联合可行域」。
专业化的代价会传导到临时键合材料	Brewer Science 的 Hamed Derami：附着太低会分层、模量太高会引入应力、TTV 会影响 RDL 均匀性；从封装 v1 到 v2 就可能要换材料；wafer→panel 的要求更严	成立。这一段把「基板专用化」的隐性成本具体化了：一辆料号变动会牵动上游化学品配方。
玻璃基板的难点不在玻璃，而在界面	Applied Materials 的 Poulomi Mukherjee：铜填充 TGV 与玻璃 CTE 不同；仅降低 liner 的 CTE 不够，模量太高就无法吸收应变；低 CTE + 低模量 liner 才减少开裂	这是全文工程含量最高的一段。它说明玻璃基板能否替代有机基板做超大 body，取决于界面工程而不是玻璃本身——这一点在大多数讨论玻璃基板的材料里被忽略。
设备必须在工艺路线收敛之前就投入	Lam Research 的 Prahalad Parthangal：行业尚未收敛到真正的范式，需要更多投资与开发；Amkor 的 Suresh Jayaraman：人人自建方案，投了某个架构未必能移植	成立，且是真正的风险点。原文只用了两句话带过，但它的资本含义最大：这是典型的「先建产能、后知需求结构」。
有产能不等于有供给	资格认证取决于能否复现特定层叠、材料体系、尺寸与良率；封装越贵，检测与过程控制越要前移	方向成立，但原文低估了它的估值含义。如果产能必须按层数/尺寸/材料体系重新认证，那么「产能利用率」这个指标在先进封装基板上的解释力会明显下降，行业更应看已认证产能的构成而非总量。
CPO 把封装洁净度要求推到了新量级	光学件不像普通 die；电子封装里可容忍的微量污染会在微透镜阵列处衰减光；有的架构用折射率匹配环氧、有的要求干净空气腔	成立。这是「光学进封装」对 OSAT 的真实门槛之一：它把封装从机械/电气问题变成了光学洁净度问题。
汽车走向相反方向	Amkor 的 Prasad Dhond：车规主力仍是传统 wire-bond，材料体系由更低成本与更高可靠性驱动，wettable flanks 提升可检性	成立，但原文没有点出它的产能含义：同一条产线要同时服务「容忍高成本换密度」的 AI 客户与「要 20 年资格历史、极致成本」的车规客户，成熟产能可能被高价订单挤走，而车规客户无法快速切到最先进方案。

三、关键数字清单

• 三种 core 结构、4 / 6 / 8 层 core：Shinko 给出的有机基板 core 分型；客户已要求把被动件嵌入 core 做电源完整性。
• 一套设计规则要跨三个制造窗口：客户架构、OSAT 组装规则、基板厂工艺极限。
• 三种组装工艺：标准 mass reflow、激光辅助键合、热压键合（TCB）。
• 两代封装 = 一次材料更换：从封装 v1 到 v2 就可能需要重新设计临时键合材料。
• 一个界面参数决定玻璃成败：liner 的 CTE 与模量。
• 九方陈述：Prismark、Intel Foundry、Shinko、Amkor、Brewer Science、Applied Materials、Lam Research、Synopsys、Mitsubishi Chemical Group。

四、我的评述（原文没有的判断）

1. 全文其实是三段归因，最后一段才是风险所在。 基板专用化 → 材料与工艺窗口专用化 → 设备与设计数据基础设施被迫专用化。前两段是技术描述，第三段才是资本支出与组织协作的风险。原文用「设备商可能要在不知道最终量产组合的情况下先投入」一句带过，但这一句的分量比前面所有材料细节都重。

2. 「已认证产能」应当被视为一个独立的、目前不可观测的指标。 如果基板厂的闲置产能必须按层数、body size、材料体系重新认证，那么行业数据里最常被引用的「产能」与「利用率」对先进封装基板的指导意义会下降。谁能先给出「按架构分类的已认证产能」口径，谁就能更早看到供给瓶颈。

3. 汽车与 AI 的双轨压力，本质是同一资产的产能挤占，而不只是「优化目标不同」。原文把它描述为两个平行的需求方向，我认为更准确的判断是：在 total capacity 有限且认证周期很长的前提下，AI 的高价订单会优先占用最新产能，车规客户被迫停留在成熟方案——这对车规客户是成本优势，对整个产业链则意味着先进产能的构成会越来越偏向 AI。

4. 「设计文件更具体」这条门槛的本质是一个知识产权悖论。 供应商必须暴露足够信息让下游做系统级热/电/力分析，但不能暴露自己的工艺差异。原文引用「黑盒」比喻点到了矛盾，但没有给出可行的中间态——我认为最现实的路径是标准化的材料本构参数格式（公开表）+ 工艺窗口签名（NDA 内），前者解决可分析性，后者保护竞争差异。这是全文最值得跟踪的一条。

5. 原文对玻璃基板的判断可以被压缩成一句话：玻璃能不能替代有机基板，取决于 liner 能不能同时低 CTE 又低模量。 这是一个非常具体的材料科学命题，比笼统讨论「玻璃 vs 有机」有价值得多。它同时意味着：玻璃基板的进展会更像一次材料突破，而不是一次产能扩张。

6. 值得警惕的一处表述习惯：原文把「可行性」与「经济性」反复并置（技术上可行 ≠ 良率可行 ≠ 经济上可行）。这三层区分是本文最有方法论的贡献——它提示读者，凡是看到「已实现」「已演示」的字样，都应该追问落在哪一层。

五、可采信度分层

• 高（物理机制或公开事实）：CTE 不匹配与 liner 模量对开裂的影响；临时键合材料的附着–模量–TTV 三角取舍；面板级封装对材料热机械稳定性的更高要求；CPO 对光学洁净度与对准的额外要求；车规仍以 wire-bond 为主；内嵌被动件进入 core 的电源完整性需求。
• 中（方向可信、量化缺失）：「有产能不等于有供给」的实际约束强度；玻璃基板与面板级的量产时间表；设备投资风险的量级；基板价值增速快于出货量的具体幅度。
• 低（内部判断）：各家对「范式尚未收敛」程度的判断；「第二供应源需要再认证一整套工艺」的具体周期与成本。

六、原文没有回答的问题

1. 每增加一层、每放大一档 body size，成本与良率各变化多少？原文只给了方向，没有曲线。
2. 玻璃基板的量产时间表与实测良率是多少？
3. 面板级封装的良率现状如何？（这是「wafer→panel」这条路径能否成立的关键）
4. 「已认证产能」在行业统计里是否可观测？如果不能，应该用什么替代指标？
5. 三个「黑盒」之间的信息交换，现实中最接近可落地的中间态是什么形态？

七、原文内部值得注意的几处

1. 「先引用、后介绍」的编排。 文中先出现「Bhatt 把材料商、设备商与晶圆厂描述为各自独立的黑盒」，下一段才通过引语正式介绍 Sanjiv Bhatt（三菱化学集团）。按逐字转载原则保留原样，读者不要误以为是两个人。
2. 同样的观察也可以看作一个提示：这篇综述里的多数判断来自会议演讲，因此「谁在什么场合说的」往往比「说了什么」更值得注意——本文中相当一部分数字（层数、core 类型、工艺路线）来自供应商自己的会议展示。

八、与本站其他文章的连接

• 先进封装通识：https://marvinlee.cn/posts/a-masterclass-on-advanced-packaging/ —— 本文所讨论的基板、interposer、RDL 的基础。
• Intel EMIB vs TSMC CoWoS：https://marvinlee.cn/posts/advanced-packaging-intels-emib-vs/ —— 桥接方案与 interposer 方案的直接对照，对应文中「bridge / fan-out 减少对大硅 interposer 依赖」。
• SK 海力士的先进封装与 EMIB/HBM：https://marvinlee.cn/posts/sk-hynix-advanced-packaging-emib-hbm/ —— 大 body 与 HBM 贴近逻辑的封装实例。
• AMD / 高通的新封装动向：https://marvinlee.cn/posts/amd-qualcomm-debut-new-packaging/ —— 客户侧封装架构的演进。
• AI 瓶颈正在移向先进封装：https://marvinlee.cn/posts/the-ai-bottleneck-is-moving-to-advanced/ —— 与本文「产能≠供给」的判断同源。
• Chiplet 架构与测试插入：https://marvinlee.cn/posts/ai-chiplet-architectures-redefining-test-insertions/ —— 文中「检测与过程控制必须前移」的另一面。
• SEMICON Taiwan CPO 全记录：https://marvinlee.cn/posts/semicon-taiwan-cpo/ —— CPO 对 OSAT 的实际要求（洁净度、对准、新设备）。
• 硅光代工层：https://marvinlee.cn/posts/silicon-photonics-foundry-layer/ —— 光电共封装如何改变封装厂的工艺清单。
• 机架级系统总览：https://marvinlee.cn/posts/system-level-overview-scale-up-ai-racks/ —— 从系统视角看基板与封装的位置。

九、一句话结论

基板行业正在从「造够数量」变成「造对那一种」，而这一步的代价是：材料、载具、组装工艺、设备与设计数据全部要从通用走向专用——其中最贵的一环，是设备必须在路线收敛之前就下注。