Measuring Supply Currents in PCB — 在印刷电路板上测量供电电流（Stanford 博士论文精读）

Stanford 2008 博士论文（James Alden Weaver）：在 PCB 上测量供电电流的新方法、探索性验证与真实问题应用。英文原文 + 中文模块化解读，正文配图无遗漏。

发表于 2026/08/03

作者 Marvin Lee

216 分钟阅读

本文为 James Alden Weaver 的斯坦福博士论文 Measuring Supply Currents in Printed Circuit Boards（2007 年 11 月答辩，© 2008）。结构为 正文（英文原文，逐页保留版面与全部配图）+ 模块化解读（中文，DeepSeek 生成，非翻译），方便中英对照、按需深读。全部 54 张原文配图已随文嵌入，无遗漏；无付费墙，全文完整。

第一部分：正文（Original Article / 英文原文）

MEASURING SUPPLY CURRENTS

IN PRINTED CIRCUIT BOARDS

A DISSERTATION

SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING

AND THE COMMITTEE ON GRADUATE STUDIES

OF STANFORD UNIVERSITY

IN PARTIAL FULFILLMENT OF THE REQUIREMENTS

FOR THE DEGREE OF

DOCTOR OF PHILOSOPHY

James Alden Weaver

November 2007

James Alden Weaver

I certify that I have read this thesis and that in my opinion it is fully adequate,

in scope and quality, as a dissertation for the degree of Doctor of Philosophy

(Mark Horowitz) Principal Advisor

I certify that I have read this thesis and that in my opinion it is fully adequate,

in scope and quality, as a dissertation for the degree of Doctor of Philosophy

(Robert Dutton)

I certify that I have read this thesis and that in my opinion it is fully adequate,

in scope and quality, as a dissertation for the degree of Doctor of Philosophy

(Simon Wong)

Approved for the University Committee on Graduate Studies.

Abstract

To realize the full performance potential of CMOS integrated circuits, the power

networks supplying them must supply sufficient current, both transient and steady

state, so that on-chip supply voltages remain within specified bounds. MOS transistor

scaling has resulted in decreased supply voltages and increased circuit density. Since

total power dissipation has remained unchanged or even increased, the combined

result is a large increase in supply current and its time rate of change, making the

design of power networks increasingly difficult. Measurements of voltages and

currents in power networks are required to develop good design and simulation

practices and to diagnose problems that arise in real systems.

This thesis presents a method that enables transient supply currents to be measured

at the package to printed circuit board interface. The approach measures the magnetic

fields generated by current carrying conductors. A simple induction loop is used to

measure the magnetic fields. We demonstrate that such a device can be made small

enough to measure PCB vias on 1 mm spacing, have a measurement bandwidth of 2

GHz, and can detect repetitive current changes as small as 6 µA/ns. This sensitivity is

sufficient to detect supply current fluctuations in real printed circuit boards. Finally the

method is applied to investigate the power network behavior for a large integrated

circuit.

Acknowledgem

ents

Without the help and encouragement of many people, completing this thesis would

not have been possible. Above all, I want to thank my family, particularly my wife

Cheryl, for their support. Their steady encouragement, patience and willingness to

listen were providential. I also owe a debt of gratitude to Nick McKeown for setting

me on the path that lead back to Stanford and, eventually, to this work.

Numerous individuals have contributed to shaping this thesis. My Advisor, Mark

Horowitz, was instrumental in keeping the work moving forward and focusing it down

to a manageable scope. In addition, Robert Dutton, Simon Wong and James Harris

deserve great thanks for their help in vetting the experimental work as it progressed

and in reviewing the manuscripts of this thesis. I would also like to thank Greg

Watson, David Siadat, Aalap Shaw and Missy Kitlas for their help and support.

Without it, developing the experimental hardware would have been much more

difficult than it was. Finally, I want to thank Tom Lee. His boundless enthusiasm and

encouragement was the perfect antidote for those times when I thought perhaps all was

lost.

This work was funded in part by the FCRP Focus Center for Circuit & System

Solutions (C2S2, www.c2c2.org) under contract 2003-CT-888. The support of Cisco

Systems is also gratefully acknowledged.

Table of Contents

Chapter 1

Introduction……………………………………………………………………………………1

Chapter 2

Background…………………………………………………………………………………….3

2.1

The Power Delivery System…………………………………………………………………3

2.2

The Importance of Power Integrity……………………………………………………….9

2.3

Voltage Measurement Methods…………………………………………………………..13

2.4

Proposed Current Measurement Method………………………………………………14

Chapter 3

Design Analysis…………………………………………………………………………….19

3.1

The Magnetic Field Surrounding PCB Vias………………………………………….19

3.2

Sensor Design…………………………………………………………………………………..23

3.3

Measurement Limits………………………………………………………………………….26

3.4

Effects on the Measured Circuit………………………………………………………….29

Chapter 4

Initial Measurements……………………………………………………………………..33

4.1

First Test: An SSTL Registered Buffer………………………………………………..33

4.1.1

Test Fixture Description……………………………………………………………..34

4.1.2

Measurement Methods and Results………………………………………………37

4.2

Second Test: A Commercial Ethernet Router Board……………………………..43

4.2.1

Description of Test Fixtures………………………………………………………..43

4.2.2

Measurement Methods and Results………………………………………………45

4.3

Summary………………………………………………………………………………………….52

Chapter 5

An Application Example………………………………………………………………..53

5.1

Description of the Approach………………………………………………………………54

5.1.1

The Test Device…………………………………………………………………………54

5.1.2

The Test Board………………………………………………………………………….56

5.1.3

Measurement Methods……………………………………………………………….60

5.2

Measurement Results…………………………………………………………………………64

5.2.1

Field Measurement…………………………………………………………………….65

5.2.2

Current Measurements………………………………………………………………..68

5.3

Summary………………………………………………………………………………………….77

Chapter 6

Conclusion……………………………………………………………………………………83

6.1

Directions for Future Work………………………………………………………………..84

6.2

Final Thoughts………………………………………………………………………………….86

Appendix A

CAM Test Board……………………………………………………………………….89

List of Figures

Figure 2.1 – Typical Power Supply Network………………………………………………………..5

Figure 2.2 – Supply Voltage and Current Trends of High Performance Processors……6

Figure 2.3 – IC Package Evolution………………………………………………………………………7

Figure 2.4 – PCB Cross-section under BGA Package……………………………………………8

Figure 2.5 – CMOS Inverters……………………………………………………………………………10

Figure 2.6 – Inductive Loop Location………………………………………………………………..16

Figure 3.1 – Cross Section of Via and Plane Pair in Region A………………………………20

Figure 3.2 – Top View of Via and Induction Loop………………………………………………21

Figure 3.3 – Loop and Via Pair…………………………………………………………………………23

Figure 3.4 – Geometrical Gain Factor………………………………………………………………..24

Figure 3.5 – Effect of Misalignment in x……………………………………………………………25

Figure 3.6 – Effect of Misalignment in y……………………………………………………………25

Figure 3.7 – Bandwidth of Resistively Terminated Loop with Integration……………..28

Figure 3.8 – Air-core Transformer…………………………………………………………………….29

Figure 3.9 – Plane Impedance Test Structures…………………………………………………….31

Figure 4.1 – Test Fixture Schematic Diagram……………………………………………………..35

Figure 4.2 – Test Fixture Assembly Drawing……………………………………………………..36

Figure 4.3 – Photograph of Test Fixture…………………………………………………………….37

Figure 4.4 – Frequency Response of 1 mm Square Probe…………………………………….38

Figure 4.5 – Loop Output Voltages for VDD/VSS Vias 45/46………………………………39

Figure 4.6 – Field versus Distance…………………………………………………………………….39

Figure 4.7 – Output Pin Current Measurements…………………………………………………..41

Figure 4.8 – VDDQ Pin Current Measurements………………………………………………….42

Figure 4.9 – VSSQ Pin Current Measurements……………………………………………………42

Figure 4.10 – Planar Loop and Insertion Site………………………………………………………44

Figure 4.11 – Planar Loop Insertion in PCB……………………………………………………….44

Figure 4.12 – Planar Loop Frequency Response………………………………………………….45

Figure 4.13 – Calibration Site and Recovered Current Signals………………………………47

Figure 4.14 – Measured CAM VDDQ Pin Current………………………………………………48

Figure 4.15 – Measured CAM VDD Pin Currents……………………………………………….48

Figure 4.16 – CAM VDD Pin Current Distribution Across Package………………………49

Figure 4.17 – Peak Loop Voltage vs. Insertion Depth for VDD/VSS…………………….50

Figure 4.18 – Peak Loop Voltage vs. Insertion Depth for VDDQ/VSSQ………………..50

Figure 4.19 – Effect of VDD Bypass Capacitors…………………………………………………51

Figure 5.1 – Top View of Test CAM Package Pin-out…………………………………………56

Figure 5.2 – Test Board Block Diagram…………………………………………………………….57

Figure 5.3 – Footprint and Via Field under DUT…………………………………………………58

Figure 5.4 – Test Board Bypass Capacitor Placement………………………………………….60

Figure 5.5 – Loop Positions for Measurements……………………………………………………62

Figure 5.6 – Blank PCB Test Locations……………………………………………………………..65

Figure 5.7 – Electromagnetic Field Solver Results with Signal Vias……………………..67

Figure 5.8 – Electromagnetic Field Solver Results with Ground Vias……………………68

Figure 5.9 – Total VDD and VSS Currents…………………………………………………………70

Figure 5.10 – Average Per Pin VDD Currents…………………………………………………….71

Figure 5.11 – Bypass Capacitor Current Contribution………………………………………….73

Figure 5.12 – Fractional Contributions of Bypass Capacitors……………………………….73

for Pins L11 & A2………………………………….75

I∂

∂

…………………………………………………….75

I∂

∂

Figure 5.15 – Power Spectrum of Aggregate VDD Current………………………………….77

Figure 5.16 – Distribution of VDD Pin Currents…………………………………………………79

Figure 5.17 – Distribution of VSS Pin Currents…………………………………………………..80

Figure 5.18 – Distribution of Bypass Capacitor Currents……………………………………..81

Figure 5.19 – Distribution of Power Plane Currents…………………………………………….82

Figure 6.1 – Cylindrical Loop Armature…………………………………………………………….85

Figure A.1 – TCAM Test Board…

……

List of Sym

bols

The magnetic field vector.

The magnitude of the magnetic field at a point in space.

Cox

The unit area gate capacitance of an MOS transistor.

The velocity of light in a vacuum.

Distance in the plane of an induction loop, normalized to the width of the

loop: x/W.

The center to center spacing, or pitch, between two vias in a printed circuit

board. Also, the unit spacing of a uniform two dimensional array of vias in

a printed circuit board.

The differential surface normal vector of an area.

The skin depth of a conductor: the point at which the strengths of the

δS

electric and magnetic fields of an electromagnetic wave penetrating a

conductor fall to one over the base of the natural logarithm.

The via spacing normalized to induction loop width: D/W.

The electric field vector.

The electric field intensity at which velocity saturation occurs in an MOS

transistor.

The relative dielectric constant of a material.

εr

The frequency of a signal or time varying quantity (e.g. voltage) in Hertz.

The height of an induction loop used to sense the time rate of change of

magnetic flux linking its area.

IDSAT

The drain current of an MOS transistor operating in saturation.

The current in an electric circuit.

Icap

The vector of printed circuit board bypass capacitor currents to be

measured.

Ipin

The vector of integrated circuit package pin currents to be measured.

Iplane

The vector of currents contributed by the printed circuit board power plane

to individual vias.

Ivia

The current passing through a printed circuit board via.

The current density field vector.

The surface current density field vector.

The inductance of an electric circuit.

The channel length of an MOS transistor.

The mutual inductance between two circuits.

The matrix of mutual inductances between multiply linked circuits.

The magnetic permeability of a material.

The magnetic permeability of a free space.

µo

The Poynting vector, indicating the direction of propagation of an

electromagnetic wave.

The resistance of an electric circuit.

The drain to source resistance of an MOS transistor.

The resistivity of a material.

tpLH

The propagation time of a digital circuit when the output transitions from

low to high.

tpHL

The propagation time of a digital circuit when the output transitions from

high to low.

Vcap

The vector of induction loop voltages induced by currents in bypass

capacitors.

VDD

The supply voltage or voltage rail for CMOS circuits.

VDDQ

The supply voltage or voltage rail for output drivers of CMOS integrated

circuits.

The threshold voltage of an MOS transistor.

Vfi

The voltage induced in an induction loop when the loop is fully inserted at

a location of a printed circuit board.

Vhi

The voltage induced in an induction loop when the loop is partially inserted

at a location of a printed circuit board.

Vout

The induced voltage in an induction loop used to sense the time rate of

change of magnetic flux linking its area.

Vpin

The vector of induction loop voltages induced by currents in the package

pins of an integrated circuit.

vSAT

The carrier saturation velocity in the channel of an MOS transistor.

VSS

The source voltage or voltage rail (usually the ground reference) of CMOS

circuits or integrated circuits.

VSSQ

The source voltage or voltage rail (usually the ground reference) of output

drivers of CMOS circuits or integrated circuits.

∂









The normalizing induction voltage:

∂





The width of an induction loop used to sense the time rate of change of

magnetic flux linking its area.

Wmos

The channel width of an MOS transistor.

The angular frequency of a signal or time varying quantity (e.g. voltage) in

radians per second.

Distance normal to the plane of an induction loop, normalized to the width

of the loop: y/W.

Chapter 1

Introduction

Over the last two decades, we have seen enormous progress in silicon technology.

The drawn channel lengths of MOS transistors have fallen by over an order of

magnitude from 1 µm to 65 nm, and 45 nm processes are in development. At the same

time, improvements in silicon processing have reduced defect densities to the point

where 1.5 cm square dies are commercially viable. The increase in performance of the

resulting integrated circuits has been breathtaking. Single purpose devices have given

way to large, multi-function devices, and entire systems on a chip are being

investigated. The increase in operating speed has been equally impressive. Decreased

CMOS circuit delays have allowed internal clock frequencies to increase from tens of

Mega Hertz to several Giga Hertz. The resulting increase in performance has opened

up entirely new applications for digital logic.

But this performance has come at a cost. The increase in circuit densities allows

designers to place an ever larger number of circuits on a die, and the result has been

ever greater complexity of the on-die system. At the same time, the combination of

large die and advanced silicon processes has significantly increased the cost of

bringing a new chip to market. It is not uncommon for the mask set for a large

Application Specific Circuit, or ASIC, implemented in a modern CMOS process to

cost many millions of dollars. Required times to market, however, have not decreased.

The combination requires that large chips be correct by design. While significant

progress has been made in circuit and system simulation and verification, the

development of simulation tools to estimate dynamic power dissipation has lagged.

This leaves system designers without the necessary tools to ensure that their designs of

power delivery networks are adequate. Their only recourse is to over-design these

networks. This must change if the benefits of improved MOS technology are to be

fully realized. Industry and the academy must collaborate to develop adequate

dynamic power estimation tools.

As these tools are developed, there will be a need for experimentally measured

data for their validation. Measurements of both voltage and currents in power deliver

networks will be required. This thesis presents a method for measuring dynamic

currents in power networks by measuring the magnetic fields created by these

currents. The location chosen to demonstrate the technique was the supply connection

between a modern ball grid array package and the underlying printed circuit board.

The method, however, is general and could be applied in other locations. In Chapter 2,

we will take a detailed look at the difficulties involved in the design of power delivery

systems and the origins of these difficulties. The utility of current measurement will be

discussed, and the basic measurement technique introduced. Chapter 3 then presents a

design analysis, showing the method is feasible. We analyze the magnetic field

behavior, develop the basic design equations, and estimate the measurement limits.

Then in Chapter 4, we present the results of exploratory measurements made to test

the method. The results show that the method is viable: measurement bandwidths of 2

GHz can be achieved, with measurement inaccuracies of approximately ten percent.

Following this, in Chapter 5, we demonstrate the application of the technique to a real-

world problem. We measure the dynamic supply currents for a CAM memory and

discuss the implications of these data for power system design. Finally, Chapter 6 we

will discuss the possibilities for the further development of the technique.

Chapter 2

Background

While continued technology scaling has been good for chip performance, it has

also made formerly simple tasks, like supplying power to these chips, much more

difficult. This chapter will look at the problem of engineering a power supply system

for modern integrated circuits. Section 2.1 first provides an overview of the

components that are involved in delivering power to the chip and explains how they

are configured. Having described the power delivery system, Section 2.2 describes the

requirements on this system, and the simulation tools that are used to try to ensure the

integrity of power networks. Since simulation tools need to be validated by

measurements, Section 2.3 then describes different techniques for measuring the

quality of the voltages in the power system, including methods that measure the end

points on-silicon, which matter the most. In situations where the voltages in the

system do not match simulations, or show poor behavior, it is often useful to measure

where the current is flowing in the system, especially in the section from the PCB

through the package. It is the measurement of this current that has been difficult in the

past, and Section 2.4 describes how a simple inductive loop can be used to provide

essential information for debugging power supply problems.

2.1 The Power Delivery System

To begin, let’s look at the components of a typical power supply for an integrated

circuit (IC). Figure 2.1 shows an IC mounted on a printed circuit board (PCB), and an

accompanying simple electrical circuit model. As the circuits on the IC die function,

they draw both AC and DC current from VDD and return it to VSS. These currents

then pass into the on-die power distribution networks, then through the IC package

and into the distribution networks in the PCB, eventually reaching the power supply.

At each stage of this journey, fluctuations in the VDD to VSS voltage can occur. The

on-die VDD and VSS networks are characterized by significant resistance, owing to

their small dimensions. The resulting R

drop creates supply voltage changes for both

AC and DC supply currents, and managing this drop is a major challenge for IC

designers. In contrast, inductance is the main characteristic of IC package voltage

distribution nets. This inductance originates from the fact that the VDD and VSS

networks are physically separated and the VDD/VSS current loop thus encloses a non-

zero area. The resulting inductance creates supply voltage changes which can be large

for rapid changes in supply current. Minimizing this inductance is one of the major

objectives of good package design. In modern high-performance printed circuit

boards, the power networks are usually copper planes and are thus distributed LC

transmission line structures. Voltage drops along these structures are created by the

chip’s AC supply currents. To reduce the magnitude of these voltage drops, so called

“bypass” capacitors are placed across the VDD/VSS networks. These capacitors

source charge to the VDD network when the IC demands more current. This reduces

the rate at which current in the PCB network must change, and so reduces voltage

fluctuation. Unfortunately, these capacitors themselves contain series inductance and

resistance, which limits their response. Nonetheless, they are an essential part of a well

designed power system, and are most effective when placed near IC packages. Bypass

capacitance can also be placed across the VDD/VSS networks on silicon to perform a

similar charge supply function. Addition of this on-die capacitance is often required in

high performance digital integrated circuits.

Figure 2.1. Typical Power Supply Network

From the foregoing discussion, it’s clear that power network impedances,

particularly on-die resistance and package inductance, must be reduced to limit power

supply voltage noise. The extent of the required reduction is determined by the

magnitude of the supply current and its time rate of change, and it is here that MOS

device scaling has had a major impact. Channel lengths have been reduced by more

than a factor of ten over the last decade, and power supply voltages have fallen from a

once ubiquitous 3.3V to values as low as 1V. Power density has increased only

moderately, but the increased circuit density made possible by scaling has encouraged

circuit designers to increase the number of circuits on a die. As a result, power

dissipation per die has remained constant or in many cases increased. The combination

has produced very large supply currents and time rates of current change. Figure 2.2

shows the feature size, supply voltage and power dissipation trends for high

performance processors over the last 25 years [HAP05]. Power dissipations of 100W

or more are now common, with supply voltages of around 1.2V. This corresponds to a

total DC supply current of 80A or more. Even in the more moderate realm of

application specific circuits (ASICs) supply currents of 40A or more are not

uncommon for large, high performance ASICs, and values of

on the order of

I∂

∂

1×108 A/sec have been estimated for some designs.

Figure 2.2. Supply Voltage and Current Trends of High Performance Processors

The advent of such large currents and the resulting need to reduce package

inductances has driven an evolution in IC package design. Figure 2.3 shows the

progression of this process. The traditional plastic quad flat-pack package (PQFP),

once an industry standard, has formed pins around the perimeter of the package for

PCB attachment. The pins connect to a lead frame inside the package which carries

power and signals inward to the edge of the die. Small bond wires connect the ends of

the lead frame to pads around the perimeter of the die. On-die metal layers then

distribute power across the die area. Since the VDD and VSS leads are carried from

the package perimeter in to the die edge, the VDD/VSS current loops enclose large

areas, and large inductances are the result. The opportunities to reduce these

inductances are limited: more VDD/VSS pins can be used, at the expense of signal

pins, and/or a finer lead pitch can be used, subject to the limits of PCB assembly

technology. Furthermore, the bond wire attachment around the perimeter of the die

Figure 2.3. IC Package Evolution

As IC packaging technology has evolved, so too have high performance printed

circuit boards. Figure 2.4 shows a cross-section through a modern PCB under a BGA

package. Routed power networks have been replaced with solid copper power and

ground planes, and for high current supplies, these planes are placed immediately

adjacent to each other with no intervening signal traces. This minimizes the VDD/VSS

current loop area and resulting inductance, and lowers the impedance of the

power/ground network. To accommodate BGA packages, an array of vias are placed

under the BGA to connect the package balls to the PCB power/ground planes and to

signal traces. PCB bypass capacitors are most effective when placed near the source of

charge consumption [AWC03]. Since the core power balls are located in a block

centered under the die, bypass capacitors are often placed on the back side of the

board, directly behind the BGA and are connected across the VDD/VSS vias. Again,

this minimizes current loop area and thus the series inductance between the

capacitance and the package balls. The resulting VDD and VSS currents are also

shown in Figure 2.4. VDD current flows into a VDD via from the VDD plane and

from any bypass capacitor on the backside of the PCB. The sum of these currents then

passes into the BGA package ball. Similarly, the VSS current from a package ball

passes into the VDD via, and thence flows into the VSS plane and any bypass

capacitor attached to the via.

Figure 2.4. PCB Cross-section under BGA Package

For AC power currents with frequencies above 14 megahertz, a VDD/VSS plane

pair forms a parallel plate waveguide structure. The currents are carried on the plane

surfaces facing each other, and the waveguide completely contains the resulting

electric and magnetic fields. While the VDD/VSS plane pair can be located anywhere

in the thickness of the PCB, the pair supplying power for IC core logic is often located

near the center because designers feel that this strikes a balance between plane to

package inductances and bypass capacitor to plane inductances. The planes and bypass

capacitors together form a complex electrical system which can have numerous

resonant modes. These modes can drastically increase supply network impedance and

increase supply noise, so steps must be taken to limit their effects. The distribution of

bypass capacitors of appropriate values across the PCB can help [SAF99], and using

lossy capacitors can also be beneficial [ZH02]. The use of high dielectric constant

layers between the VDD/VSS plane pair to form a distributed bypass capacitor is also

under development, and can be very beneficial [MHC03]. The use of ferro-magnetic

coatings on the plane surfaces has also been studied as a way to lower the Q factor of

power system resonances [WT05].

2.2 The Im

portance of Power Integrity

From our review of power distribution it’s clear that distributing large supply

currents with high voltage quality can be difficult and potentially expensive. The

important questions are what level of voltage quality is required and what design

methods can be used to estimate the voltage quality that can be expected from a given

design. In addressing the question of voltage quality, we must first understand the

effects of supply voltage variation on CMOS circuits. In digital circuits, extreme

fluctuations in supply voltage can cause malfunctions, but owing to the nonlinear

nature of their operation, most digital circuits can tolerate relatively large variations in

power supply voltage and still function correctly. The largest impact of supply noise is

variation in gate delay times, which results in reduced system performance. The

source of this variation can be understood using the simple circuit shown in Figure

2.5. Here a CMOS inverter drives another CMOS inverter. Assuming the two inverters

are not connected by a long metal route, the load on the driving inverter is essentially a

capacitance, CL, composed of the drain to bulk parasitic capacitances of the driving

transistors Q

P and Q

N and the input capacitance of the driven inverter. The driver

output voltage, VO, rises when CL is charged from VDD through the effective output

resistance of Q

P and falls when CL is discharged to ground through the effective output

Figure 2.5. CMOS Inverters

In well designed CMOS gates, the input switching threshold is very close to

VDD/2 and changes minimally with variation of VDD. Thus the delay time of the

driving inverter in Figure 2.5 can be taken as the time required for VO to rise (or fall)

to VDD/2. Exact calculations for this time are quite complex (see for example

[Hor83]), but a simple first order approximation is adequate for our purposes. We

assume that the driving MOS transistor and the load capacitance form a simple RC

circuit and therefore that voltage VO will rise (or fall) exponentially with time. So the

low-to-high and high-to-low delay times are tpLH = ln(2)ROPCL and tpHL = ln(2)RONCL,

respectively. In a well designed gate, these times will be roughly equal. To estimate

the effect of supply noise, we need to understand how ROP and RON change with VDD.

Since modern short channel MOS transistors operate in velocity saturation for all but

the

lowest

values

VDS,

can

use

the

approximation

that

where IDSAT is given by ([SKM84], [TKM88]):

VDD

DSAT

(

)

−

(2.1)

(

)

SAT

mos

DSAT

−

The saturation velocity, critical electric field value, and unit area gate capacitance

(vSAT, ESAT, Cox) depend on the silicon process node, and the channel width and length

(Wmos,l) depend on transistor geometry. Combining this with the expressions for

delay then gives the result:

















(2.2)

)

ln(

−





pHL

pLH

SAT

mos

Since the transistors are assumed to be heavily velocity saturated, the term in the

(

)

square brackets is near unity, and so delay scales as

. Other

−

approximations for IDSAT can be used ([TN98], [GM01]) and empirical expressions for

RO have been proposed [Wor89], but all show that delay depends on supply voltage.

Because of this, supply noise creates uncertainty in propagation times which can

require the insertion of extra delays and reductions in clock frequencies in order to

close timing in digital systems, at the cost of reduced performance. To achieve high

of nominal.

performance, supply voltage tolerances have often been tightened to ±

With supply voltages hovering around 1 volt, this translates into a variation of ±

mV. For analog circuits the constraints can be even tighter. Supply voltage noise in

analog circuits can cause numerous problems such as spurious spectral components in

oscillators, and jitter in phase locked loops and clock recovery circuits. A noise limit

of 25 mV peak-to-peak on analog supply rails is not uncommon. Meeting such a

requirement can be difficult when such circuits are used in mixed-signal chips

containing both digital and analog circuits.

With such tight constraints on supply voltage, extensive use of numerical

simulation tools is now essential to the design of power networks that perform

adequately and are cost effective. The nature of the problem, however, poses

challenges to these tools. Transient currents in the supply networks of digital

integrated circuits are produced by the activity of CMOS circuits that are highly non-

linear in nature. On the other hand, the interconnect portion of the supply network is a

large, linear system containing both lumped and distributed circuits. Thus we are faced

with a dilemma. The non-linear circuits must be simulated in the time domain with

tools such as Spice, whereas the interconnect portion is most efficiently simulated

either in the time domain using a fast linear solver or in the frequency domain. Using

Spice to simulate the entire power system produces untenably long simulation times.

Furthermore, the supply interconnect is a large system that often cannot be sectioned

into smaller pieces without significant loss of simulation accuracy. This is particularly

true of on-die power grids and ball grid array packages. As a result, the sheer size of

the resulting problem can overwhelm many simulation tools.

To make power system simulation a tractable problem, it is usually necessary to

introduce simplifications to reduce the problem size. One such simplification is to

divide the problem into two simulations [BPC01]. The CMOS circuit operation is

simulated with a constant supply voltage using Spice, and the resulting supply currents

applied to the interconnect model, which is simulated using a fast linear simulator. The

resulting voltage fluctuations at the circuit level are then used to determine the effects

on performance. Another approach is to instantiate a small number of CMOS circuits

as pilots and replicate identical neighboring circuits as current sources controlled by

the pilot circuits. The circuits and interconnect are then simulated together. This

technique can be particularly useful in simulating the supply voltage noise generated

by large blocks of simultaneously switching output circuits. Simplifications are also

often required in dealing with the interconnect model, since the full interconnect

model may be so large that simulation time is too long even with the use a fast linear

solver. To further reduce simulation time, model order reduction can be employed.

The transfer function of a complicated model will contain many higher order terms

that do not contribute materially to the response of the model to the applied stimulus.

Model order reduction attempts to simplify the model by eliminating these terms while

leaving the relevant terms intact. What is relevant will depend on the spectrum of the

stimulus and the degree of accuracy required.

Necessary as they are, these simplifications bring with them the possibility of

appreciable inaccuracy in the predicted voltage supply noise at the circuit level.

Partitioning the problem into separate non-linear and linear simulations introduces

error. Iteration reduces the error, but the iteration may diverge. Simulation using pilot

circuits controlling blocks of current sources will give erroneous results if the block

size is too large. Finally, model order reduction can give good results but can also

produce models that are unstable and/or non-casual. Unstable models are fairly easily

detected as they produce wild oscillations in the results as simulation proceeds. Non-

causality is a far more insidious problem. Non-causal models exhibit output response

behavior that is not the result of the input stimulus. The effect is often subtle and

difficult to detect, but leads to considerable errors in simulation results. Some

modeling tools (e.g. Broadband Spice from Sigrity Inc., ADS from Agilent Inc.) now

attempt to enforce both stability and causality in the models they produce. To do so,

they make (hopefully) small changes to the transfer function to ensure that the

resulting model is stable and causal.

2.3 Voltage M

easurem

ent M

ethods

With many possible sources of error, it is clearly desirable to validate simulation

and modeling methods by comparing the simulated supply voltage behavior at critical

points in the power system to the corresponding values measured in real systems.

These measurements have traditionally been made at the VDD and VSS pins of the

integrated circuit package(s) using an oscilloscope. When die sizes were small (≤ 4

mm2) and operating frequencies low (≤ 50 MHz), such measurements were perfectly

adequate. The continued advancement of CMOS technology has produced large die

operating at frequencies into the GHz range. As operating frequencies increased and

the noise spectrum widened, the distance between measurement point and ground

reference had to be decreased to reduce the loop area subject to stray noise reception.

The allowable distance today can be as small as a few millimeters. At the same time,

these larger die require much larger packages, and, as we have seen, the

die/package/PCB combination forms a complicated system whose internal behavior is

not readily observable from voltage measurements across the package pins. Certainly,

supply voltage fluctuations at the printed circuit board level must stay within

prescribed limits, and measurements on the PCB are required to verify this. But on-die

measurements of supply voltage are now required to verify power system integrity at

the circuit level and validate simulation results.

Several schemes have been advanced to make on-die supply voltage

measurements. One of the simplest is the method used by Darnauer et al. [DCS99]. In

this approach, matching 400Ω PMOS resistors connect adjacent locations on the VDD

and VSS networks to signal tracks routed out to two package pins. Differential

measurement across these pins gives the time varying supply voltage at the monitoring

point. Using this method, the authors investigated the affects of bypass capacitor

placement and package technology on supply voltage noise. On-die measurements

have also been made. Muhtaroglu et al. [MTR04] demonstrated measurement circuits

that can detect supply voltage overshoots and undershoots that exceed programmable

limits over an adjustable time window. Using a number of these circuits linked by a

scan chain, the authors collected voltage noise magnitude and time distribution data

for a large microprocessor die. Petrescu et al. [PPV06] have proposed a family of

measurement circuits, including a voltage measurement circuit that uses a seven bit

DAC controlled via a scan chain and a fast synchronous comparator to measure supply

voltage level and droop. On-die sub-sampling oscilloscope heads for supply voltage

measurement have been demonstrated by both Takamiya et al. [TMN02] and Inagaki

et al. [IDT06]. Inagaki obtained good agreement between simulation and measurement

of supply noise on a test chip. An interesting approach has been demonstrated by Alon

et al. [ASH05]. In this scheme, dual samplers and simple, VCO based AD converters

are used to extract the autocorrelation function of the supply voltage noise. From this,

the power spectral density of the noise is obtained as the Fourier transform of the

autocorrelation function. All of these schemes, particularly those using on-die

samplers, can provide valuable measurement data for validating the performance of

power distribution networks and the quality of the supply voltage at the circuit level.

2.4 Proposed Current M

easurem

ent M

ethod

Voltage measurements tell us much about the integrity of a supply network. Our

understanding can, however, be extended if we have knowledge of the transient

currents in the supply networks. It is the passage of these currents through the non-

zero impedances of the power networks that generates the supply voltage noise. If

measured supply voltage noise differs significantly from the predictions of simulation,

a likely cause is an erroneous impedance calculation. Knowledge of the actual network

impedances can help to locate the errors. Absent measured transient current data,

methods to date for determining supply network impedance under operating

conditions have relied on various means of estimating currents from voltage

measurements ([KHR04], [WCH03], [WLS04]). The difficulties and potential

inaccuracies of these methods can be eliminated if fine-grained measurements of

transient currents can be made. By measuring the transient currents in the VDD/VSS

pins of an integrated circuit package and combining these data with on-die voltage

measurements, the transfer impedances between the pins and the die could be directly

obtained. These results could then be compared to the values predicted by simulation.

Also, package pin current measurements would allow system designers to access the

effectiveness of PCB bypass capacitance when lack of information about chip

internals prevents simulation.

These current measurements require a current sensor of small physical size that

has a wide measurement bandwidth, ideally 1 GHz or more. With such a wide

bandwidth, the sensor should also have low internal noise so that an adequate signal to

noise ratio (SNR) can be achieved. Furthermore, measurements should have minimal

impact on the measured circuit. All of these requirements argue for the use of a single

turn inductive loop as a sensor. Such sensors have been proposed for IDDT testing

([NIA04], [ABS05]). The basic idea behind the approach is simple. A current carrying

conductor generates a surrounding magnetic field. If a small, single turn loop is placed

in this magnetic field, changes in the conductor’s current will induce a voltage across

the loop, and from this voltage, the AC current can be found. These loops can be made

very small, and so have low self inductance. This gives a high upper measurement

frequency. Furthermore, they are a metal resistor with a few milliohms of resistance,

so they have no flicker or shot noise and only a small amount of thermal noise.

Effectively, the noise floor is set by the voltage measurement instrumentation. Finally,

since the induced voltage grows linearly with frequency while the random noise in the

instrumentation grows as the square root of frequency, SNR does not degrade with

increases in measurement bandwidth.

Figure 2.6. Inductive Loop Location

There are, of course, penalties associated with induction loops. They cannot

measure DC fields, and so DC currents cannot be measured. Since we are interested

primarily in high frequency transient currents, the lack of a DC reading is tolerable.

Induction loops also have a large magnetic aperture. The result, in this application, is

that currents from multiple adjacent package pins will contribute to the voltage

induced in the loop. For verification of simulation results, this effect can be predicted

and thus presents no fundamental problems. For stand alone current measurements,

measurements at multiple locations can be made, which allows removal of this

magnetic crosstalk. Figure 2.6 shows how an induction loop can be inserted in a

printed circuit board to measure core VDD/VSS via currents. A non-plated hole is

placed midway between a VDD and VSS via pair. A small loop is then inserted into

this hole with the loop plane lying in the plane containing the vias. The VDD and VSS

currents are in opposing directions and so create circular magnetic fields threading the

loop in the same direction. This increases the magnitude of the induced loop voltage.

Finally, note that all of the VDD/VSS BGA ball currents are carried through that

portion of the vias between the VDD/VSS plane pair and the package. The section of

the vias below the planes will carry current if there are bypass capacitors attached to

the via ends on the backside of the PCB. This current can be measured by inserting the

loop only up to the planes and taking measurements. This value can then be subtracted

from the reading with the loop fully inserted to recover the BGA ball currents.

Chapter 3

Design Analysis

Using a single turn inductive loop to measure via currents depends completely on

the magnetic fields surrounding the vias and on the response of an induction loop to

these fields. This chapter develops the understanding necessary to implement a

practical sensor. Section 3.1 deals with the magnetic field surrounding the vias, while

Section 3.2 considers the behavior of the induction loop sensor. Section 3.3 then

explores the measurement limits of this design. Both upper and lower frequency limits

are considered. Finally, Section 3.4 looks at the effect of probing on the measured

circuit.

3.1 The M

agnetic Field Surrounding PCB Vias

The proposed measurement approach relies on the fact that a current carrying

conductor is surrounded by a magnetic field, and the intensity of this field is

proportional to the magnitude of the current. If a small, single turn loop is placed in

this field, changes in the conductor’s current will induce a voltage across the loop

∫∫

. To make practical use of this principle,

given by Faraday’s Law:

∂

•

=∂

loop

however, we must know the spatial distribution of the magnetic field. This can be

done with a straightforward application of Maxwell’s equations to the via/PCB

configuration of Figure 3.1. As shown, high performance printed circuit boards have

ground (or power) planes as their next to outermost layers to reduce electromagnetic

radiation from the board. Thus between the VDD/VSS plane pair supplying the vias

we want to measure and each outer surface there is at least one (possibly several) solid

plane(s). The skin depth, δS, of AC electric and magnetic fields in these layers is given

by [RWV67]:

where ρ = 17.2 nΩ-m for copper, f is the field frequency, and µ = µο = 4π × 10−7 H/m

for the materials used in printed circuit boards. Typical printed circuit board planes are

18 µm thick copper. Setting δS = 18 µm and solving for f gives f ≅ 14 MHz. Thus over

most of the frequency range of interest it will be the case that δS is much less than the

thickness of the PCB metal layers, and we can approximate the pairs of planes as

perfect conductors which completely contain electric and magnetic fields between

them.

To predict the magnetic field produced by a via’s current we proceed as follows.

Figure 3.1 shows a single current carrying via passing through a plane pair. Since the

skin depth is much less than the thicknesses of the planes, we assume that the

conductivity of the planes approaches infinity.

Figure 3.1. Cross Section of Via and Plane Pair in Region A

The governing equations are Maxwell’s equations, repeated here for reference (SI

units):

∂

−

∇

•

∇

∂

∇

•

∇

∂

Figure 3.2. Top View of Via and Induction Loop

To calculate the loop response we first assume that the current densities in all

power and ground planes are equal in the vicinity of the loop, and therefore,

power/ground pairs induce no signal in the loop. The induced voltage as a function of

loop location is then easy to calculate. Figure 3.2 shows a top view of a current

carrying via and an induction loop with its center located at a distance r from the via

center and rotated through an angle θ. The loop has a width W in the x direction and

height h parallel to the via’s axis. The voltage, Vout , induced in a loop is derived using

Faraday’s

Law

Induction

with

the

magnetic

field

intensity

given

. Since either of the two loop terminals can be defined as the

)

(

via

positive terminal, we will choose the definition that eliminates the minus sign from

Faraday’s Law.

Then:

∂

∫

∫∫

•

(

)

cos

∂

out

−

∂

∫

(3.1)

via

∂

−















∂









via

∂







−















Hence the mutual inductance, as a function of x and y, is:



















(3.2)

)

(







−











Since ferromagnetic materials are rarely used in printed circuit boards, the system is

linear, and we can superpose the loop voltages created by individual vias to obtain the

total loop voltage.

Figure 3.3. Loop and Via Pair

The loop center coordinates are (D/2, 0). Using these values of x and y, equation (3.1)

can be rewritten as:









−

out





(3.3)

∂

and

where

∂

This ratio can be considered a geometrical gain factor and its value is plotted against δ

in Figure 3.4.

Figure 3.4. Geometrical Gain Factor

This plot would imply that the loop width, W, should be made as large as possible.

PCB manufacturing tolerances, however, make it impossible to perfectly position the

loop. To assess the effects of loop misalignment, we can rewrite equation (3.1) in

terms of displacement from the ideal position of (D/2, 0). This gives:









−

(

)

(

)

(

)

(

)

Vloop









−

(

)

(

)

(

)

(

)









(3.4)

and

where

Here, δ and V* have the same definitions as in equation (3.3), and x and y are the

displacements from (D/2, 0). Equation (3.4) is plotted against χ in Figure 3.5 and

against ψ in Figure 3.6 for δ = 2, 3, 4 and 5. The plots show that a value of δ = 4,

corresponding to a loop width of W = D/4, is a reasonable design compromise. The

output voltage of a loop this size changes by less than 10%

of its centered value for x

or y displacements of half a loop width, and the geometric gain factor has a reasonable

value of 2.04.

			D/ D/ D/ D/		W = 2 W = 3 W = 4 W = 5

Figure 3.5. Effect of Misalignment in x

			D/W = 2 D/W = 3 D/W = 4 D/W = 5

1.5

Figure 3.6. Effect of Misalignment in y

To build the loop, we can use standard PCB technology, and employ a 76 µm (3

mils) wide copper trace on a 100 µm (4 mils) thick FR4 substrate to form the loop.

The most commonly used BGA ball pitch is 1 mm, so the active loop width should be

250 µm (10 mils). The overall width is 100 + 2 × 76 = 402 µm (16 mils). Happily, a

500 µm (20 mils) diameter non-plated hole can be reliably drilled between vias on a 1

mm pitch, so this loop can be inserted into printed circuit boards.

3.3

easurem

ent Lim

its

Constructing a loop appears feasible, so next we need to address the question of

measurement limits. This is really two questions: what is the minimum detectable

signal and what is the overall measurement bandwidth. Let’s first look at the question

of minimum detectable signal. The loop itself is nothing more than a metal film

resistor. A 3 mm long (i.e. h = 3 mm) loop of 76 µm wide, half ounce (18 µm) thick

copper trace enclosing an air gap of 250 µm has a resistance of less than 1 mΩ. So the

loop generates no shot or flicker noise and only a miniscule amount of thermal noise.

The overall noise floor is thus set by the measurement instrument(s) used. A

commonly used instrument is a high performance real time sampling oscilloscope,

such as the Tektronix TDS7704B. This unit has a sampling rate of 20 Gs/sec and a

front side bandwidth of 7 GHz. Its equivalent noise voltage is roughly 1 nV/

Hz, and

assuming a first order roll-off, this gives a total equivalent noise voltage of 105 µV.

Using a signal to noise ratio (SNR) of 1 as the detection limit, the minimum detectable

signal level is 105 µVrms. The sensitivity of the loop will depend on the effective loop

height, h. This will depend on the exact board thickness and VDD/VSS plane pair

location, but high performance PCB thicknesses are in the 2.5 mm to 3 mm range.

With h = 3 mm, equation (3.3) gives a mutual inductance of M = 613 pH. For a

sinusoidal VDD/VSS via current

where f is the sinusoid’s frequency,

∂

2π

and Io is its amplitude. Therefore, the root mean square signal voltage is

. Arbitrarily setting Io = 10 mA, the minimum required frequency is

3.9 MHz. The corresponding required peak

is 0.25 mA/ns. We can then

I∂

∂

normalize this to give a minimum

requirement of 0.75 mA/ns/mm of via pair

I∂

∂

length. Finally, note that for measuring repetitive events, we can average a large

number of samples. This improves the signal to noise ratio by

N, where N is the

number of samples averaged, and lowers the minimum required

I∂

∂

Now let’s take up the question of measurement bandwidth. This is largely a

question of identifying the upper measurement frequency. The loop will be connected

to the input of a measurement instrument which has purely resistive input impedance.

Figure 3.7 shows the resulting equivalent electrical circuit. The resistance, R, is the

input resistance of the instrument, and the inductance, L, is the self inductance of the

loop. The loop response is then determined as follows.

∂

For sinusoidal excitation:

)

∂

via

The transfer function is:

)

(

)





)

(

)



Therefore the transfer impedance is:

(





)

(

via

(

)

, the loop response is that of a differentiator.

Thus for frequencies

Therefore, below this frequency the loop voltage must be integrated to recover the via

current. Above this frequency, the loop voltage is proportional to sensed current.

While it might be possible to recover and process current data in two regimes, it is

cumbersome, and the SNR will degrade because the signal amplitude is fixed above

the break, while the random noise will grow as

f. Therefore, we would like the

break frequency to equal or exceed our desired upper measurement frequency of 1

GHz. Current measurements can then made by integrating the induce loop voltage.

This integration produces a quasi low-pass response:









)

(





(3.5)





)

(





via

This is plotted in Figure 3.7. The response is only quasi low-pass because of the

minimum signal requirements considered earlier; we cannot measure DC currents.

Figure 3.7. Bandwidth of Resistively Terminated Loop with Integration

Since R = 50Ω for all high frequency measurement instruments, the bandwidth

question comes down to what is the self inductance, L, of the loop. Since the loop

height needs to equal or exceed the thickness of the thickest PCB we want to measure,

we set h = 3 mm. Then, since the loop is very much longer than it is wide, we can treat

it as two parallel conductors. The inductance can then be calculated using the formula

[Gro40]:









≅









(3.6)

5.1





where L is in nano-henries, h is the loop height in centimeters, d is the center to center

spacing of the two conductors, B is the width of the conductors and C is the thickness

of the conductors. Using the dimensions of our loop: h = 3 cm, d = 250 µm + 76 µm,

B = 76 µm and C = 18 µm, the inductance is L = 3.2 nH. With R = 50Ω, this gives a

break frequency of 2.5 GHz. which exceeds the minimum desired upper limit of 1

GHz. The loop construction approach thus seems feasible, and we can simply integrate

the loop voltage. Instruments like the Tektronix TDS7704B sampling oscilloscope can

output their digitized measurement data, so this integration can be done numerically.

3.4 Effects on the M

easured Circuit

Finally, we should look at what this measurement scheme does to the measured

circuit. There are really two effects to be considered. The first is the effect a resistively

terminated loop has on the VDD/VSS circuit impedance. The second is the effect the

500 µm non-plated hole has on the impedance of the underlying VDD/VSS plane pair.

Taking these in order, we will first look at the effect the loop has on via circuit

impedance. Referring Figure 3.8, we see that a VDD/VSS via pair and the loop form

an air core transformer with the loop as the secondary winding and negligible series

resistance. Using the sign convention shown in the figure, the voltages and currents

can be described by the equations for a transformer:

where L1 is the VDD/VSS via circuit self inductance, L2 is the loop self inductance and

M is the mutual inductance between the via pair and the loop.

Figure 3.8. Air-core Transformer

For steady state sinusoids these equations can be written as:

Noting that

, we can solve for the impedance seen at the primary, giving:

−









(

)

(

)

−

)







(3.7)

(

)

(









Notice that resistively terminating the loop lowers the effective VDD/VSS circuit

inductance and that the magnitude of the reduction increases with frequency. To

calculate the via circuit self inductance, we treat the circuit as consisting of two

circular conductors spaced a uniform distance apart. The inductance can then be

calculated using the formula [Gro39]:









−









(3.8)

where L1 is in nano-henries, l is the via length in cm, d is the via pitch and r is the via

radius. The effects on Z1 are greatest when L1, L2 and M are large, so we will here use

the maximum board thickness of 3 mm. The via pitch is d = 0.1 cm, and the via radius

is an industry standard 25 µm (10 mils). Equation (3.8) then gives L1 = 2.4 nH. The

mutual inductance can be calculated using equation (3.2), giving M = 613 pH, and

equation (3.6) gave L2 = 3.2 nH. Then using equation (3.7), the relative reduction in

via circuit inductance is:





∆

(

)

−





GHz

(

)

Similarly, the added resistance as a fraction of the original inductive reactance is:





∆

(

)





GHz

(

)

For shorter via lengths or lower frequencies, these values are even smaller. Thus the

presence of the terminated loop has a minimal effect on VDD/VSS via circuit

impedance.

Finally, we need to look at the effect the presence of the 500 µm non-plated hole

has on the impedance of the VDD/VSS plane pair. Keep in mind that the scale here is

very small: less than 1 mm, so the one-eighth wave length frequency is ~20 GHz in

FR4 material. Therefore, we cannot use a simple transmission line approach to assess

the effects. What we can do is use commercial field solver tools to examine the effect

on the VDD via to VSS via impedance. Figure 3.9 shows two test structures used to

examine the effect of the hole. Both consisted of 10 cm square, 18 µm thick VDD and

VSS planes separated by an FR4 dielectric (εr = 4) and a single 250 µm diameter VDD

via surrounded by four 250 µm diameter VSS vias at a 1 mm pitch. As shown, these

vias were surrounded by industry standard 760 µm (30 mils) diameter anti-pads as

required to prevent shorting. The first structure contained only vias and anti-pads,

while the second structure contained a 760 µm anti-pad for the probe hole, located

between VDD via A and VSS via B.

Figure 3.9. Plane Impedance Test Structures

Two commercial simulation tools, PowerSI® and PowerDC®, both from Sigrity Inc.,

were then used to calculate the impedance seen looking into vias A and B and the DC

resistance between these vias. For the AC test, two different plane separation distances

were tested: 51 µm (2 mils) and 102 µm (4 mils). For the DC resistance calculation, a

voltage source was connected between the VDD and VSS planes at a point collinear

with vias A and B, 4.5 cm from via A and 4.4 cm from via B. The change in

impedance over the frequency range of 10 MHz to 1 GHz produced by the presence of

the probe hole was imperceptible, as was the change in DC resistance.

Chapter 4

Initial M

easurem

ents

From the preceding design analysis, it appears that a single turn induction loop can

be a practical sensor for measuring AC currents in printed circuit board vias. What we

must do now is demonstrate, using a real sensor, that we can accurately measure AC

via currents. In the process, we should also validate the basic conclusions of the

preceding section regarding magnetic field fall-off with distance. The final test is to

in real printed circuit boards are actually measurable.

determine if the values of

I∂

∂

Two sets of tests were conducted to answer these questions. In the first, we developed

a fixture to provide a “best case” measurement environment to test the basic ideas. In

the second test, we created a loop probe which would work in a modern printed circuit

board and modified a board from a high end Ethernet router to allow it to be inserted

between power and ground vias under BGA packages to make current measurements.

The remainder of this chapter details the methods and results of these two tests.

4.1 First Test: An SSTL Registered Buffer

In this first test, a commercially available 14 bit registered buffer with SSTL2

outputs created the currents for measurement. This made it easy to create a known

pattern of activity. By measuring the voltage across the SSTL2 output termination

resistors, the true output currents could be determined. The accuracy of the magnetic

measurements of output currents could then be checked by comparison to these known

values. Long vias were used to allow use of a relatively crude probe and to allow easy

manipulation of the probe around the vias. The principal goals of this test were to

verify the expected magnetic field behavior in the vicinity of the vias and to show that

via currents can be accurately measured using an inductive loop. An additional goal

was to measure the break frequency of the loop. This frequency is fixed by the loop

self inductance, which is proportional to loop area. The loop used was relatively large:

1 mm × 1mm. Therefore, if its break frequency equaled or exceeded the desired value

of 1 GHz, the same should be true for a smaller loop that could be inserted in a real

printed circuit board.

4.1.1 Test Fixture Description

To create a known pattern of electrical activity, the circuit shown in Figure 4.1 was

used. All 14 outputs of a 74SSTL16857 registered buffer were terminated through

50Ω resistors to 1.25V, half the value of the 2.5V core (VDD) and output (VDDQ)

supply levels. This established a symmetric output voltage swing about 1.25V and a

symmetric output current swing about zero. A frequency dividing D flip flop drove all

14 inputs to the buffer so that all of the buffer outputs toggled simultaneously at half

the rate of the buffer input clock. Separate clock inputs were provided for the buffer

and the D flip flop, and these were driven by a dual output pulse generator. The two

clocks could be separately enabled or simultaneously enabled at the same frequency

with a phase difference between 0 and 360 degrees. This allowed the affects of the

buffer clock and the data inputs on VDD supply current to be independently

examined.

Figure 4.1. Test Fixture Schematic Diagram

To effectively use the circuit of Figure 4.1, a fixture had to be designed which

would emulate the vias found in typical printed circuit boards while allowing insertion

and manipulation of a loop probe. Also, the probe had to be easy to construct. The

resulting design is shown in Figure 4.2 and Figure 4.3. The 74SSTL16857 buffer, U1,

was mounted on a 0.8 mm thick interposer board. To create an array of industry

standard vias, the pins on each side of U1 were connected with surface traces to a

double row of 250 µm (10 mil) diameter wire columns connecting the interposer board

to a four layer base board. These columns emulated the industry standard 10 mil

diameter vias used under BGA packages. The double row allowed easy access to all

vias, and the 1.27 mm × 1.27 mm spacing used is a via pitch used under some BGA

packages. A 1.5 mm air gap was maintained between the boards, and this allowed

insertion of a 1 mm square induction loop. The back of the interposer was a ground

plane, and the base board contained 2.5V and ground planes with the ground plane

facing the interposer. The output terminating resistors were placed on the back of the

base board.

Finally, a loop probe was created by winding a single turn of #28 AWG magnet

wire around a 1 mm square wooden mandrel. A 50Ω coaxial cable with a 0.8 mm

outside diameter carried the induced loop voltage signal out of the fixture. Precision

XYZ translation stages were used to manipulate the probe. The current signatures of

all vias were acquired by positioning the loop at the surface of each via and recording

the loop output voltages. These voltages were measured using a Tektronix 7704B real

time sampling oscilloscope, which had a 50Ω input impedance, a 20 G/sec sampling

rate, and a 7 GHz front end bandwidth. The digitized data were exported for

subsequent analysis.

Figure 4.2. Test Fixture Assembly Drawing

Figure 4.3. Photograph of Test Fixture

4.1.2

easurem

ent M

ethods and Results

As discussed in Section 3.3, the location of the induction loop break frequency

relative to the desired measurement upper limit determines how the loop output

voltage data must be processed to recover via currents. Thus the first task was to

determine the frequency response of the induction loop probe. This was done by

driving the loop probe with an identical loop and using a vector network analyzer to

measure S21 from the driving to the receiving loop. The result of this measurement is

shown in Figure 4.4. It’s clear from this result that the break frequency was 2 GHz, so

the loop output voltage was proportional to dB/dt for excitations at and below this

frequency. As a cross check, a TDR was used to measure the self inductance of the

loop. The value measured was 3.9 nH. With a 50Ω termination, this gives an R/L

break frequency of 2.04 GHz, which agrees well with the VNA measurement. Since

the break frequency exceeded the minimum required upper measurement limit of 1

GHz, current measurements were obtained by numerically integrating the loop output

voltage data and scaling the results by the calculated mutual inductance between the

vias and the loop. The resulting upper measurement limit was 2 GHz.

1000

Figure 4.4. Frequency Response of 1 mm Square Probe

In order to calculate the mutual inductance between a via and the loop, the

decrease in magnetic field intensity with distance from the via must be known. The

analysis of Section 3.1 predicts that the field intensity should be proportional to the

inverse of this distance. A simple test was conducted to validate this prediction. With

the data inputs to U1 static, U1’s internal clock tree alone generated sufficient current

to produce measurable loop signals at VDD/VSS vias 45/46 (see Figure 4.2). The loop

output voltages obtained are shown in Figure 4.5. The signals were very nearly mirror

images of each other, indicating that the via currents were of equal magnitude and

opposite polarity. Since the surrounding data input vias were quiescent, vias 45 and 46

formed an isolated current doublet. The field surrounding this doublet was then used

to measure the decrease in field intensity with distance. Figure 4.6 shows the measured

peak loop output voltage (and therefore magnetic field) fall-off with distance both in

and perpendicular to the plane of the doublet, normalized to the surface of via 45. Also

plotted in the figure is the theoretical near field response. As can be seen, the fall-off

exhibited near field behavior in both cases.

Loop Output (Volts)

8e-08

Figure 4.5. Loop Output Voltages for VDD/VSS Vias 45/46

Figure 4.6. Field versus Distance

With the field fall-off behavior verified, a via to loop mutual inductance of 480 pH

was calculated, and initial measurements of output pin currents were attempted. The

results showed that there was significant interference from the VDDQ and VSSQ vias

embedded in the output via field. To remove this interference, the matrix, M, of

mutual inductances between each measurement location and vias 25 through 48 (see

Figure 4.2) was calculated using equation (3.2) of Section 3.1. The maximum distance

involved was 15.3 mm. This was less than one-eighth of a wave length at 1 GHz, so

quasi-static conditions were assumed. Measurements were made at each of vias 25

through 48 giving a voltage vector. This vector was pre-multiplied by the inverse of

the mutual inductance matrix and integrated with respect to time to recover the vector

of individual via currents. The sign convention adopted was that current out of the

buffer pins was positive. The results for the output pin currents are shown in Figure

4.7, plotted in red. The known output currents obtained from voltage measurement

across the terminating resistors were all within 2%

of each other and are plotted in

blue in the figure. The magnetic measurements for vias 6, 10, 15 and 19 showed a

systematic error of 20%

while the errors in the remaining measurements were 10%

less. The average error for all 14 outputs was about 10%

. U1 was housed in a lead

frame package and emitted significant EMI, similar to that described by Dong et al.

[DDH04]. A large magnetic field component of these emissions was parallel to the

interposer ground plane. Since this plane was of finite extent, circulating currents

developed which allowed the field to leak through, creating the systematic

measurement error. Modern BGA packages use planes to distribute power and

microstrip or stripline traces to distribute signals, so these packages emit minimal

amounts of EMI.

100

ents

Figure 4.7. Output Pin Current M

easurem

Figure 4.8 and Figure 4.9 show the current measurements obtained for the VDDQ

and VSSQ pins, respectively. Note that since the buffer output switching activity was

well understood, the DC levels of the VDDQ and VSSQ currents could be restored. At

each of the points labeled A and B in Figure 4.8, the sum of VDDQ currents is within

of the sum of the actual output pin currents (14 × −21mA = −294 mA), while at point

C the VDDQ current sum is within 5%

of the correct value of zero. At each of the

points labeled A and C in Figure 4.9, the sum of VSSQ currents is within of the sum

of the actual output pin currents (14 × 21mA = 294 mA), while at point B the sum is

within 5%

of the correct value of zero. Overall, the measurement accuracy was

reasonably good.

100

Figure 4.8. VDDQ Pin Current Measurements

100

Figure 4.9. VSSQ Pin Current Measurements

4.2 Second Test: A Com

ercial Ethernet Router Board

The results of the first test were encouraging: the loop probe had an upper

measurement limit of 2 GHz, and signal and supply currents were successfully

measured. The questions then were how to insert a loop between VDD and VSS vias

in a real printed circuit board and what were the minimum detectable currents. To

answer these questions, a second set of tests was conducted. We constructed a planar

loop which would fit into a non-plated hole drilled between two vias in a printed

circuit board, and modified a board from a high-end commercial Ethernet router was

then modified to include 80 of these measurement sites distributed under 4 different

BGA packages. A probe calibration site was also created. After determining the

measurement bandwidth of this new probe, we used it to make measurements at all 80

sites with Ethernet traffic passing through the router. The overall goal was to

demonstrate that via currents could be successfully measured in a real environment.

4.2.1 Description of Test Fixtures

The first task was to create a practical induction loop and a workable method for

inserting it into an industrial printed circuit board (PCB). Standard PCB technology

was used to create the loop which consisted of a 76µm (3 mil) wide copper trace on a

100µm (4 mil) thick FR4 substrate. Square pads at the end of the loop allowed

attachment of a 50Ω semi-rigid coaxial cable. To create an insertion site, a 500µm (20

mil) diameter non-plated hole was drilled between power and ground via pairs. A

diameter of 500µm is the largest that can be reliably drilled between vias at a 1mm

spacing, which is the most common BGA ball pitch. Since the analysis of Section 3.2

showed that a via pitch to loop width ratio of 4 gave a good compromise between

signal sensitivity and insensitivity to positional misalignment, the loop internal width

was made 250µm (10 mil). The loop height was 3 mm, but the effective loop height

for sensing is the distance from the top surface of the board to the supply/ground

planes for the power/ground vias being measured. This was either 1.4 mm or 2.6 mm,

depending on the voltage level measured. Figure 4.10 shows a drawing of the probe

Figure 4.10. Planar Loop and Insertion Site

Figure 4.11. Planar Loop Insertion in PCB

Figure 4.12. Planar Loop Frequency Response

In addition to this upper measurement limit, a practical lower limit exists. This

limit is reached when the loop output voltage can no longer be distinguished from the

noise in the measurement instrumentation. To determine this limit, as well as to

reconfirm the one-over-distance magnetic field fall-off, a calibration site was included

in the router’s printed circuit board. This consisted of two vias spaced at 1mm pitch

with a 500µm diameter probe hole between them. The PCB stack-up was unaltered in

this location, so the vias pierced but did not connect to the 14 power and ground

planes of the board. Top surface traces routed at right angles to the line joining the

vias allowed connection of a coaxial cable, and bottom surface traces also routed at

right angles to the line joining the vias allowed connection of a 50Ω surface mount

resistor across the bottom end of the vias. Figure 4.13 shows a drawing of the

calibration site. A signal generator created a 10 mA amplitude sinusoidal current

through the resulting circuit. A mutual inductance of 600pH from vias to loop was

calculated assuming a one-over-distance field behavior, and loop output voltages were

numerically integrated and scaled by this value to recover current waveforms. The

loop voltage measurement device was the same Tektronix 7704B oscilloscope used in

the first test (see Section 4.1.1).

Initial measurements showed the zero input signal noise in the oscilloscope to be

well described by a normal distribution. Therefore, for repetitive signals, averaging

should improve the overall signal to noise ratio by sqrt(N) where N is the number of

samples averaged. Experimentation showed that using 2048 averages, a 100kHz

10mA current could be recovered with good accuracy. This corresponds to a peak

of 6µA/ns. For single shot acquisitions, a frequency of 5 MHz would be

I∂

∂

required, corresponding to a peak

of 0.3 mA/ns. Again, these results agree

I∂

∂

reasonably well with the predictions of Section 3.3. Finally, measurements were made

at 1 MHz and at 10MHz to check the flatness of the response, and the results are

shown in Figure 4.13. As predicted by the simple analysis of Section 3.2, the response

was flat from 10 MHz down to 100 kHz. The amplitude values obtained were all

within 2%

of the correct value of 10mA.

0.4

Figure 4.13. Calibration Site and Recovered Current Signals

With the measurement limits of the probe determined, current measurements were

made at the sites on the modified Ethernet router board. Output voltages of 2mVpp or

greater were found at all sites. As an example, Figure 4.14 shows the measured current

signature of a VDDQ pin of a content addressable memory (CAM) as 37 outputs

switched simultaneously from low to high. The output resistance of the drivers and the

PCB trace impedance were both 50Ω, and there were a total of 7 VDDQ pins at 2.5

volts. The receivers presented approximately a 4pF load at the output end of the lines.

The calculated peak current was (37/7) × (2.5/100) = 132mA. Magnetic crosstalk was

minimal at this site, and the measured peak current matches this value. As another

example, Figure 4.15 shows the current signature of a core VDD (1 volt) pin of this

same CAM with Ethernet traffic circulating. Figure 4.16 shows the distribution of

peak VDD values for ten VDD pins distributed across the area of the package. Two

loops were used: one to provide a stable trigger from one site and one to sample the

remaining nine sites. Similarly clean measurement results were found at all 80 sites.

Figure 4.14. Measured CAM VDDQ Pin Current

300

Figure 4.15. Measured CAM VDD Pin Currents

Figure 4.16. CAM VDD Pin Current Distribution Across Package

Finally, measurements of the VDD and VDDQ via current signatures of this CAM

were used to examine the validity of the assumption that power/ground plane pairs

make no contribution to the induced loop voltage and also to examine the effect of

bypass capacitors under the CAM. In both cases, the test procedure was the same: the

peak loop output voltage was measured as a function of loop insertion depth,

measured from the back side of the printed circuit board. In other words, the loop

voltage was measured as a function of loop height, h. Figure 4.17 shows the

measurement results for the 1V VDD/VSS via pair and Figure 4.18 the results for the

2.5V VDDQ/VSSQ via pair, normalized to full insertion amplitude. Neither via pair

had bypass capacitors connected to them. For the VDD/VSS via pair, the results show

the expected behavior with depth, and the indicated VDD/VSS plane pair position was

~1.8 mm from the top surface of the board, which is reasonably close to the actual

value of 1.4 mm. There was some extraneous signal at 0.6 mm depth, and this was

exactly the depth of the VDDQ/VSSQ plane pair. This implies that this plane pair did

make some contribution to the loop signal, but the contribution was less than 10%

the total. The results for the VDD/VSS via pair also showed the expected linear

behavior with depth, and the indicated VDD/VSS plane pair position was ~2.8 mm

from the top surface of the board, which is quite close to the actual value of 2.6 mm.

On balance, the assumption that plane pairs produce a negligible signal is reasonable.

2.5

Figure 4.17. Peak Loop Voltage vs. Insertion Depth for VDD/VSS

2.5

Figure 4.18. Peak Loop Voltage vs. Insertion Depth for VDDQ/VSSQ

Figure 4.19. Effect of VDD Bypass Capacitors

4.3 Sum

ary

Taken together, the results of these two tests show that small induction loops can

be used to measure transient currents flowing through power and ground vias in real

printed circuit boards. Using standard PCB lithography, planar loops can be

constructed which are small enough to fit between vias spaced at 1mm pitch under

BGA packages and which provide a measurement bandwidth in excess of 2 GHz.

When such loops are inserted between a power/ground via pair, the resulting

sensitivity is approximately 0.2 mV/mA/ns per millimeter of current carrying via

length. This allowed a repetitive current of 6µA/ns in a 3mm long via pair to be

measured with high fidelity using an industry standard sampling oscilloscope. In a

board from a high end Ethernet router, 80 sites under BGA packages yielded clean

measurements. Where magnetic crosstalk from adjacent vias was minimal, the

measured current signatures matched expected current values to within 5%

error. For

VDD pins of a CAM memory, activity dependent transient current patterns were

observed, and the distribution of peak intensities of these patterns across the package

was measured. Furthermore, varying the effective loop height by varying loop

insertion depth validated the treatment of power/ground planes as parallel plate

waveguides for transient signals and also allowed the current contributions of bypass

capacitors to be investigated. Overall, the measurements could be used to validate

simulation results, since crosstalk effects can be accounted for in simulation.

Chapter 5

An Application Exam

ple

The results thus far show that power system currents in printed circuit boards can

be measured using an inductive loop sensor. Such loops can be made small enough to

be inserted into real printed circuit boards and yet have a bandwidth and sensitivity

adequate to sensing power network currents. Furthermore, the measurement accuracy

is reasonable; errors in the five to ten percent range can be expected. We will now

apply this technique to a real world problem and demonstrate that useful results can be

obtained. While there are many possibilities, a problem of major concern for system

designers is that of large integrated circuits with very large changes in switching

fraction. Such parts can exhibit large swings in supply current and also very large

. The power system must be designed to supply adequate charge, both

values of

I∂

∂

instantaneously and on a sustained basis, or the supply voltage will droop excessively,

leading to compromised performance or outright failure.

Critical aspects of this are the selection and placement of bypass capacitors to

provide transient charge and the number, thickness, and placement of supply and

ground planes. As discussed in Chapter 2, simulation of the power networks is a

critical part of this process. For system designers, however, the simulation and design

problems are compounded by the fact that vendors of integrated circuits are often

either unable or unwilling to provide comprehensive data on the temporal and

geometric distribution of supply currents. This forces designers to apply estimated

“worst case” stimuli in simulation. It is then uncertain whether the resulting design is

adequately robust. If the supply pin currents of problematic parts could be measured

during realistic worst case operation, this uncertainty could be removed. This is the

task addressed in this chapter. We will measure the currents in all power and ground

pins of a large integrated circuit as this part makes worst case transitions in internal

activity. The results will show the distribution of current as a function of time and the

actual values of

that reach the printed circuit board. In addition, we will see that

I∂

∂

it is possible to measure currents in both bypass capacitors and supply planes as well,

giving additional insight into the performance of the power network.

5.1 Description of the Approach

The integrated circuit selected for test was a Content Addressable Memory

(CAM), which is frequently used in Ethernet routers. This section describes the

methods used to obtain maps of the real time supply currents for this device. The

characteristics of the CAM are described in section 5.1.1, along with the reasons for

choosing this device. Section 5.1.2 then describes the test printed circuit board used to

take the current measurements. Finally, section 5.1.3 describes the methods used to

collect and process the measurement data.

5.1.1 The Test Device

As already stated, a Content Addressable Memory (CAM) was used as the test

device. This device was chosen for several reasons. First, this type of memory can

exhibit large swings in supply current to the memory core. Besides read data and write

data modes, a CAM has a search mode. In this mode, a data key is presented to the

CAM inputs, and the contents of the memory are searched for stored data matching the

key. If a match is found, an index to the location of the matching data is placed on the

outputs. The search mode is implemented by placing a match line across each row of

cells in the memory mat. The match lines are all driven high at the beginning of a

search. The input key data are then compared to the bits in each row, and if any of the

bits in a row differ from the key, the match line for that row is pulled low and a miss is

said to occur. Thus, large currents can be drawn during compares that end in a miss.

Depending on the size and organization of the memory mat and on the sequence and

rate of application of keys, very large and abrupt changes in supply current can occur.

The memory chosen had a storage capacity of 10 Mb, operated synchronously from a

500 MHz clock, and had a 1 volt core supply voltage. Thus this part is a good example

of the kind that present power system design challenges to system engineers.

A second reason for selecting this particular CAM was that it contained built-in

self test (BIST) logic capable of executing a number of different test patterns. After

the BIST logic is configured and triggered, no further manipulation of chip inputs is

required for test execution. This significantly simplified the test board: only a small

field programmable gate array (FPGA) was required to control the BIST tests. Also,

the BIST logic could be configured to loop on a particular test. This allowed for data

averaging which improves the signal to noise ratio. One of the BIST tests was

by alternating between large

specifically designed to create worst case values of

I∂

∂

numbers of consecutive misses and large numbers of consecutive matches. It is this

test that was used to create the supply currents for measurement. The algorithm for the

test is described in the following pseudo-code:

Initialization {

write_ones_to(all_locations);

write_zeros_to(last_row_of_all_blocks);

enable(all_blocks);

set_search_width_to(all_bits);

}

Test {

For(specified_loop_count) {

search_for(all_zeros, n times);

search_for(all_ones, n times);

}

Finally, the CAM chosen was contained in a 576 ball BGA package with an

organic substrate and a 1 mm ball pitch. The package technology is thus a present day

standard, and the size is large enough to present power design challenges. This

becomes clear when looking at the part’s pin-out, shown in top view in Figure 5.1,

(horizontal pin numbering follows the industry standard practice: A B C D E F G H J

K L M N P R T U V W Y). Here, the 1 volt core VDD pins are shown in red and the

VSS pins in blue. As can be seen, VDD and VSS pins are distributed across the

package area, but their density is high in a “hot spot” in the center of the package,

under the die. This is typical for large BGA packages. Supplying current to this hot

spot is a preoccupation of PCB designers because their presumption has always been

that this is the area through which the majority of the supply current passes. Yet, as

can also be seen, doing this is complicated by the large number of intervening pins. In

contrast, pins away from this area have traditionally been viewed as less effective in

supplying power. Using the chosen CAM, with the pin-out of Figure 5.1, will allow

these assumptions to be quantitatively evaluated.

Figure 5.1. Top View of Test CAM Package Pin-out

5.1.2 The Test Board

With the test device (hereafter referred to as the DUT) selected, it was then

necessary to produce a test board which would simultaneously provide a realistic

system environment and also allow the currents of all of the DUT package pins to be

measured. A block diagram of the resulting design is shown in Figure 5.2. The BIST

control pins of the DUT were driven by an FPGA; the FPGA was programmed and

controlled via an IEEE/ANSI 1149 standard JTAG bus. Since most of the DUT inputs

were unused for BIST testing and the DUT was designed to allow cascading, most of

the outputs were conveniently terminated by connecting them back to the inputs. The

few remaining outputs were terminated resistively. The output loads were thus typical

of those seen in a real system environment. An on-board clock generator provided a

500 MHz clock to the DUT and a 250 MHz clock to the FPGA phase aligned with the

500 MHz clock. The JTAG inputs were synchronized to the 250 MHz clock inside the

FPGA. Thus the operation of the FPGA was synchronized to that of the DUT. In

addition to controlling the BIST logic, the FPGA emitted a trigger output whose

transition could be precisely aligned to the start of the BIST test in the DUT. This

allowed data from multiple measurements to be coherently merged. Finally, on-board

DC-DC converters provided all supply voltages, including the 1V DUT core supply.

Figure 5.2. Test Board Block Diagram

Standard printed circuit board practices were followed to create the footprint for

the DUT on the test board as shown in Figure 5.3 (a). Surface mount pads of 500 µm

diameter were placed at 1 mm pitch to create a 24 square array of 576 contact points

for the BGA package of the DUT. Then 250 µm O.D. vias were placed interstitially

with the surface mount pads, and short surface traces joined pad to via. The vias were

place so as to create chevrons pointing diagonally away from the center of the

package. The via pattern thus created, shown in Figure 5.3 (b), results in 2 mm wide

“ways” clear of obstructing vias. This is a practice commonly used by board designers

to clear the way for current to the presumed hot spot at the center of the package.

Following the procedure described in Section 4.2, insertion sites for the inductive loop

were created by placing 500 µm diameter non-plated-through holes next to the vias. In

this case, we need to have a measurement site for each of the 576 vias. This allows

magnetic crosstalk from neighboring vias to be removed, as described in the next

section and the current in each via to be determined.

Figure 5.3. Footprint and Via Field under DUT

Placing a measurement site between every via, however, would significantly

increase the porosity of the area under the chip and could thus excessively disturb the

impedance of the power/ground plane network. To avoid this, four DUT footprints

were placed on the test board, each with 144 measurement sites. These footprints were

identical in every way (bypass capacitor placement, IO loading, etc) except for the

placement of the probe holes. In the first footprint, the measurement sites were placed

between every other via (i.e. on a 2 mm pitch), both vertically and horizontally,

starting 0.5 mm above the upper left had corner via in Figure 5.3 (b). In the second

footprint, this pattern was slipped down one via pitch vertically. In the third footprint,

the initial pattern was slipped down one via pitch vertically and to the right one via

pitch horizontally. In the fourth footprint, the initial pattern was slipped one via pitch

to the right. Thus for each footprint, the space between vias in the vertical direction

was unobstructed, and in the horizontal direction, only every other space was

occluded. The resulting increase in porosity was under fifteen percent. By taking

measurements at the 144 sites in each footprint and moving the DUT through all four

footprints, measurement data for all pins could be acquired. To enable this,

SK0576BG2701A compression sockets from DCI Corporation were used to connect

the DUT to the test board. These sockets are used on high performance integrated

circuit testers for IC characterization and have an extremely low profile and therefore

low inductance. Compressible pins are used to make the PCB to IC connection, and

when the part is fully seated, 2.6 mm of height is added. Using equation (3.8) in

Section 3.4 and the stack-up dimensions for the board, the sockets add 1.3 nH of

inductance for an adjacent core VDD/VSS via pair. This was deemed a tolerable

disturbance. The validity of this assumption will be addressed during the discussion of

measurement results in Section 5.2.

To produce an environment typical of systems in which the DUT is used, the layer

stack-up of the printed circuit board was made identical to the supervisor board of a

high performance Ethernet router. The board contained 24 layers: 8 stripline signal

layers, 8 ground planes to form the striplines, and 4 supply/ground plane pairs. Total

board thickness was 3 mm (116 mils), and the VDD/VSS plane pair for the DUT core

power was located 1.4 mm (55 mils) below the front (DUT attach) side of the board,

which is the same position these planes occupy on the Ethernet router board where the

DUT is used. Appendix A contains full documentation of this stack-up.

Figure 5.4. Test Board Bypass Capacitor Placement

Bypass capacitors were placed on the back side of the board. The capacitance

values and placement of these capacitors closely matched the implementation on

Ethernet router supervisor boards were the DUT is used. The majority of the bypass

capacitors used were 0.1 µF ceramic capacitors with an X7R dielectric and a 0201

case size. These were placed diagonally across core VDD and ground vias as shown in

Figure 5.4 (the measurement site holes are also visible in this figure). Low inductance

8 pin 2.2 µF IDC ceramic capacitors were placed at the edge of the via array. At the

corners of the via array 100 µF ceramic capacitors (not shown) were placed to provide

bulk charge storage. During testing, the worst case supply noise observed at the DUT

was 10 mV peak to peak, so this bypass strategy was more than adequate for this

application.

5.1.3

easurem

ent M

ethods

Since measurements were taken at multiple sites distributed across four distinct

footprint locations, we must have a stable reference point in time if we are to be able

to coherently combine the measurements and make sense of the results. This was

accomplished by using an FPGA operating synchronously with the DUT to set up and

initialize BIST tests in the DUT and to provide a trigger of data collection (see Figure

5.2 above). The logic inside the FPGA would watches the BIST commands being sent

to the DUT, and when the start_bist_test command is recognized, an “offset”

counter is started. When this counter reaches a preset value, the FPGA pulses its

trigger output, and a “cycle” counter is started. When this counter reaches a preset

value, another trigger pulse is issued and the counter is reset to zero and begins

counting up again. By setting the cycle counter to the length of the BIST test loop, the

offset counter could be used to both skip over the BIST initialization sequence and

position the trigger at a predetermined location within the test. For the results

discussed in this chapter, the trigger was placed at the beginning of the BIST test loop

and remained constant for all data measurements. A Tektronix TDS 7704B sampling

oscilloscope was then used to measure the output of the inductive loop at each

measurement site. Samples were collected at 8 ps intervals, and acquisition was

initiated by the FPGA trigger pulse. The presence of a stable trigger also allowed

signal averaging to be used. At each measurement site, sixteen samples of data where

collected and averaged. This improved the signal to noise ratio by a factor of four,

which was more than adequate.

The induction loop sensor used in these measurements was the same as that used

in the initial testing described in Section 4.2 and was inserted into the measurement

sites from the back side of the printed circuit board as shown in Figure 4.11 of that

section. This creates both a problem and a data collection opportunity. When the loop

is fully inserted in the printed circuit board next to either (or both) a VDD of ground

pin, the induced loop voltage will be the sum of that created by currents into the

package pin(s) and that created by currents through any bypass capacitors attached to

the vias on the back side of the board. Since there is an intervening power/ground

plane pair which can either source or sink current, the value of the package pin current

is indeterminate. To solve this problem, the approach shown in Figure 5.5 was taken.

For each measurement site, two readings were taken: one with the loop half-way

inserted, just up to the core VDD/VSS plane pair, and one with the loop fully inserted.

The package pin current data are then obtained by subtracting the first reading from

the second.

Package

Package

Figure 5.5. Loop Positions for Measurements

While somewhat tedious to execute, this method provides us with more

information about the behavior of the power network. The half insertion

measurements, if carefully executed, allow the transient currents in the bypass

capacitors to be determined, which in turn allows a quantitative assessment of their

effectiveness to be made. Furthermore, recalling the results of Figure 4.19 in Section

4.2.2, we can obtain information about the plane currents by subtracting two times the

half insertion data from the full insertion data. If the result is zero, then the entire

package pin’s current is supplied or sunk by the attached bypass current. A positive

result indicates that the plane is supplying current and a negative result that it is

sinking current. All of these data can then be plotted against the pin location to give

the distribution of these currents across the package area as a function of time.

To obtain the current value for each pin from the loop voltage measurements

requires that the magnetic crosstalk from adjacent vias be removed. Following the

approach taken in Section 4.1, the vector V of voltage measurements can be expressed

in terms of the vector I of via currents and the matrix M of mutual inductances

∂I. In general, the elements of these

between vias and measurement sites as: V = M

t∂

quantities are complex numbers, reflecting the phase effects of signal propagation over

distance. The problem becomes far simpler if we can assume quasi-static conditions,

that is, that the phase effects of signal propagation over distance are minimal and can

be ignored. The elements of M are then real numbers, and the current vector can be

∫

using simple matrix algebra. To see if the quasi-static

obtained as

−

assumption can be made, first note that the supply/ground plane pairs form a parallel

plate waveguide with spacing on the order of 100 µm and that the loop measurement

bandwidth is 2 GHz. Therefore, the propagation mode for all measurable signals in the

power system will be transverse electro-magnetic. Hence the propagation velocity will

be independent of frequency and given by

where c is the velocity of light in

a vacuum and

rε is the relative dielectric constant of the insulating material between

the power and ground plane. The test board used a fiber glass / FR4 resin composite

which had a relative dielectric constant of 4. Setting a phase shift 10%

of a period of

as the limit for the applicability of the quasi-static approximation gives a distance limit

of 7.5 mm at a frequency of 2 GHz. Since each measurement site is 0.5 mm from its

target via and the field fall-off is one-over-distance, the magnitude of interfering

signals will be reduced by a factor of

at the quasi-static limit. For

067

5.7

5.0

signals with a lower frequency, f, the distance limit increases by a factor of

(

2×

As we will see in the next section, the spectrum of the measured signals contained

essentially no energy above 100 MHz. At this frequency, the distance is four times the

diagonal length of the DUT footprint. Therefore, quasi-static conditions were

assumed. The mutual inductance matrix could then be easily computed by repeated

application of equation (3.2) in Section 3.1. Since the core power / ground plane pair

for the DUT were located very near the center of the test board’s thickness, the via

height above and below the planes was essentially the same. Therefore, a single

mutual inductance matrix can be used to recover both bypass capacitor and package

pin currents. Equations (5.1) show the sequence of calculations used to recover current

data. In these equations, Vhi are the voltages measured with the loop inserted half way

into the board, and Vfi are the voltages measured with the loop fully inserted into the

board. M is the mutual inductance matrix, and Icap, Ipin and Iplane are the current

vectors for the bypass capacitors, package pins and power planes respectively.

[

]

[

]

∫

(

)

(

)

−

cap

[

]

[

]

(5.1)

−

cap

−

cap

plane

The TDS 7704B oscilloscope gives a column vector of voltage data versus time

and it’s because of this that the transpose operators appear in the equations. Also note

that by assuming quasi-static conditions, we can do the time integration before solving

for the currents. These integrations were done numerically, using the trapezoidal

approximation, and the solutions for currents were done in MATLAB® using its left

divide function. Finally, bear in mind that since the DC levels of the currents cannot

be found using an inductive loop, the true values of the integration constants are

unknown. Therefore, the trigger point for data acquisition was set to the end of the

sequence of CAM matches (the minimum activity point), and the integration constant

for all measurements was set to zero. This provided a consistent point of reference

which allowed relative comparisons between the measurement data to be made.

5.2

easurem

ent Results

This section first describes the precursory measurements made to verify the

behavior of the magnetic field surrounding the vias in the printed circuit board under

the DUT. The second part then describes the results of applying the methods of the

previous section to measuring current in the DUT package pins. As might be expected,

a large amount of data resulted, which gave a current vs. time trace for each pin. While

this data could be used in numerous ways, the discussion will focus on three areas of

particular interest to system designers: the distribution of current across the package

pin field, the effectiveness of bypass capacitors, and the maximum / minimum values

reaching the printed circuit board.

I∂

∂

Figure 5.6. Blank PCB Test Locations

The pulse generator emitted a 10 MHz trapezoid wave with a 1 volt amplitude and 0.8

ns rise and fall times; this created a ∂I/∂t = ±(1/50Ω)/0.8ns = ±2.5 × 107 A/sec in the

via pair. The 250 µm wide inductive loop was inserted 2 mm into the board

(mechanical interference with the shorting wire prevented full insertion). Using the

values of W = 250 µm and h = 2 mm, the measurement results are predicted by

recasting equation (3.1) to use the distances from the active VDD and ground vias,

giving:









(

)

(

)

(

)

(

)

−

)







(5.3)

−

(

)

(

)

(

)

(









∂

Where:

∂

Table 1 below compares the predicted and measured results. In this table, χ1 and ψ1

are the normalized x and y distances from the driven VDD via, and χ2 and ψ2 are the

normalized x and y distances from the driven ground via. While there is some scatter

in the measurement data, the agreement with prediction is reasonable. Differences are

800 µV or less.

Field Fall-off Test Results

Table 1.

L o catio n	χ1	χ2	ψ2	P redicted V l o o p	Measu red V l o o p
Site 1	−6	−2	4	−0.7 mV	−0.9 mV
Site 2	−2	2	4	−6.0 mV	−5.5 mV
Site 3	2	6	4	4.0 mV	4.8 mV
Site 4	6	10	4	0.8 mV	0.8 mV
Site 5	10	14	4	0.3 mV	0.3 mV

As a cross check to these measurements, a field simulation was run using the

HFSS® three dimensional electromagnetic field solver from Ansoft Corporation. Two

planes were spaced at 100 µm distance to form a parallel plate wave guide, and their

edges were terminated with a perfectly absorbing layer. Two through-vias at 1 mm

pitch pierced these planes and were driven differentially using 50Ω microstrip lines

and HFSS wave-ports. To check for disturbance created by intervening signal and

VDD vias, a three by three array of vias at 1 mm pitch was placed 1 mm from the

driven pair. These vias were connected to the bottom plane but insulated from the top

plane. Figure 5.7 shows the magnitude of the magnetic field along a line half way

between two rows of signal vias. The simulated field intensities at 10 MHz, 100 MHz

and 1 GHz are plotted along with the near field prediction. As can be seen, the

simulation results for all three frequencies were essentially the same. The agreement

with the near field prediction is reasonable but not perfect, indicating that the vias may

have some effect; also, the simulation accounts for resistive losses in the copper

planes, which the simple near field prediction does not.

Figure 5.7. Electromagnetic Field Solver Results with Signal Vias

To check the affects of ground vias, which short the ground planes together, we

repeated the field simulation with the signal via array replaced by a three by three

array of ground vias connected to both planes, once again on a 1 mm pitch. The

results, shown in Figure 5.8 below, are similar to those for the signal via array, but

some differences are present. For the 100 MHz and 1 GHz frequencies, there is some

non-monotonic behavior of the field intensity near the first ground via. This suggests

the presence of a low quality factor resonance in the ground via array. Deep into the

block of vias, the field intensity falls somewhat more rapidly than in the previous case.

For the 10 MHz frequency, the resonant behavior is absent, but again, the field

intensity inside the ground via array falls off somewhat more rapidly than it does

inside the block of signal vias. The conclusion has to be that ground vias do disrupt

the magnetic field somewhat. Fortunately, as can be seen in the figures, the disruption

occurs when the field intensity is low, limiting the error in assuming near field

behavior, and except for the very center of the package the number of ground vias per

unit area is low (see Figure 5.1). Therefore, we will assume that near field behavior

applies to the magnetic field, but refinement of this treatment is an area for further

work.

2.5

Figure 5.8. Electromagnetic Field Solver Results with Ground Vias

5.2.2 Current M

easurem

ents

With the magnetic field behavior approximated as near field, the methods of

Section 5.1.3 were then used to collect measurement data at all 576 via locations while

the DUT executed the

BIST test described in that section. This test executes

I∂

∂

internally in the DUT without any activity on the input or output pins, and the

measurements showed that the input/output pins and their VDDQ and VSSQ supply

pins were quiescent. Only the input clock pins and the 209 VDD and VSS core supply

pins created transient current signatures. Data from these pins were processed

according to the methods outlined in the previous section to yield a full mapping of the

VDD and VSS pin currents over a test cycle. These results can clearly be used to

validate the predictions of simulations as well as to provide measurement data to

printed circuit board designers. As stated earlier, the focus in this work is on

measurement data that will aid printed circuit board design.

To begin the discussion, we can get a good feeling for the overall supply current

behavior, as well as a validity check on the results, by summing all the VDD pin

currents and all the VSS (ground) pin currents and plotting the results versus time.

Figure 5.9 shows just this plot. Note that in the sign convention adopted is that current

into the package is positive. Thus ground current is negative. Looking at the figure,

the overall current behavior during the BIST test is apparent. The test produces a

square pulse of current with amplitude of about 12 amperes and duration of

approximately 10 ns. The sharp rise in current occurs as the test progresses from a

series of searches resulting in matches into a series that results in misses. The current

then decreases to a value of 8 amperes and remains at this level for 240 ns. This is

followed by a sharp drop in current as a sequence of matches begins. The sum of the

VDD and VSS currents should, of course, be zero, and this sum is plotted in the

figure. While not perfect, the sum is small; its maximum value as a fraction of VDD

current during the miss sequence is 5 percent. The rapid oscillations in the waveform

are most likely the result of ringing in the package, and have a frequency of

approximately 48 MHz. The slow undulation in the VDD current results from ringing

of the bypass capacitors, and has a frequency of 14 MHz. The rise and fall times are

approximately 5 ns. Given this current behavior, we could then run another check on

the results. The average supply current could be read from the DC-DC converters on

the test board. The value obtained was 4.1 amperes. Given the 50%

duty cycle of the

VDD current square wave, this implies a peak current of approximately 8 amperes and

a minimum current close to zero, values very close to those measured.

Figure 5.9. Total VDD and VSS Currents

The general nature of the current distribution can be seen by plotting the value of

the current for each of the pins across the two dimensional array of DUT package pins

and then observing the evolution of this plot as a function of time. The resulting

sequence for the VDD pin currents is shown in multi-pane Figure 5.16. This shows the

currents just beginning to rise, at their maximum value, at their quasi steady-state

values near the end of the miss sequence and the ringing after the falling edge. The

time stamps shown are times from trigger shown in Figure 5.9. The corresponding

sequence for the VSS pins is shown in Figure 5.17. For viewing clarity, the negative

of the pin currents in plotted in this figure. After looking at these plots it is clear that

both the VDD and VSS currents are larger in the center of the package, under the die.

It is also clear, however, that significant current is carried by the peripheral pins

outside this area. We can quantify the extent of this effect by calculating the average

per pin current for pins inside the central area and the average per pin current for

peripheral pins outside of this area, and then plotting these values as a function of

time. Figure 5.10 shows the result for VDD pin currents. The central area is the area

inside the red square and contains 12 of the 89 total VDD pins. The plot shows that

during the current peak, the average per pin current is 30 percent higher for pins in the

central area than the average for peripheral pins. After the peak, during the period of

100 to 250 ns after trigger, this increases to 33 percent. Similar results were obtained

for the VSS pins.

Figure 5.10. Average Per Pin VDD Currents

Thus the current density is higher in the central area, and supplying power to this area

is important. Board designers should note, however, that considerable total current can

still be supplied by the periphery. In this case, for example, the periphery supplies

77%

of the total current while the central area supplies the remainder. The DUT

package is doing a reasonably good job of spreading the DC current load across the

package area.

To examine the effectiveness of the bypass capacitors placed behind the DUT on

the backside of the board, we can start by plotting the distribution of capacitor currents

across the area of the DUT footprint as was done for the VDD and VSS pin currents.

The result is shown in multi-pane Figure 5.18. The sign convention is that current out

of the capacitors is positive, and the time stamps are the same as in Figure 5.16 and

Figure 5.17. It is clear that bypass capacitors make a large contribution of charge

during the interval of peak current demand as the DUT transitions from matches to

misses. Then when the DUT transitions from misses back to matches, the bypass

capacitors absorb a large amount of charge as the current stabilizes. Between these

events, the capacitors make no significant contribution to VDD pin current. Notice

that the currents at the center of the left and right edges of the chip lag behind the

other currents. This is where the 2.2 µF IDC capacitors are located (vs. 0.1 µF

everywhere else), and the lag is consistent with their large value. By subtracting the

capacitor currents from the package pin currents, we can display the contribution of

the VDD plane to the package pins. This result is shown in multi-pane Figure 5.19,

where the sign convention is that current from the plane to the pin is positive. The plot

for the 16.792 ns time stamp, the point of maximum current draw, shows that the

VDD plane makes very little contribution to the pins with bypass capacitors attached

to their vias. After the peak passes and the current draw stabilizes, the plane

contributes all of the current, which is clear from the plot with the 223.992 ns time

stamp.

We can quantify the contribution of the bypass capacitors, and reveal something

rather surprising, by displaying the currents of two adjacent VDD pins in the central

area, one with a bypass capacitor attached and one without, and the bypass capacitor

current on the same graph. The result is shown in Figure 5.11 (see Figure 5.10 for pin

locations). Pin L11 (red trace) has a 0.1 µF bypass capacitor attached to its via while

adjacent pin M11 (blue trace) does not. The current of the capacitor attached to L11 is

shown with the green trace; the 14 MHz ringing results from a damped oscillation of

the capacitor and supply/ground plane circuit. After the peak current draw, the

currents in L11 and M11 converge to nearly the same value. During the peak current

draw, however, the situation is quite different. While the current through pin L11 is 50

percent larger than the current through pin M11, more importantly, the bypass

capacitor supplies 90 percent of pin L11’s current. This is a general result. Figure 5.12

shows the current for each of the bypass capacitors as a fraction of the current of the

package pin to which they are connected. There are two 3D plots: one looking from

Figure 5.11. Bypass Capacitor Current Contribution

1.60

1.40

1.20

1.00

0.80

0.60

0.40

0.20

0.00

Figure 5.12. Fractional Contributions of Bypass Capacitors

This has implications for printed circuit board design. System designers have

always assumed that if bypass capacitors were relatively closely spaced, the

intervening pins would current share. The measurement results contradict this

assumption and indicate that the preferred path for current transients is along the z axis

through the board to a bypass capacitor on the backside attached directly to the pin

via. Certainly, capacitors do supply multiple vias, but the majority of the current will

be taken by the pin to which the capacitor is directly attached.

Finally, we can use the measurement results to determine the values of

that

I∂

∂

reach the printed circuit board. Figure 5.13 shows the values of rising edge

for

I∂

∂

for

pin L11 in the central area and pin A2 at the package corner. The value of

I∂

∂

pin A2 is 15 amperes per microsecond while the value of

for pin L11 is 50%

I∂

∂

greater. This implies a variance in the values of

depending on pin location. We

I∂

∂

can quantify this by measuring the maximum value of rising edge

for each pin.

I∂

∂

plotted across the chip area. There are two 3D

Figure 5.14 shows the values of

I∂

∂

plots: one looking from the numbered side of the package and one looking from the

lettered side of the package (see Figure 5.1). The minimum value of

is found to

I∂

∂

be 5 amperes per microsecond, and the maximum value is 30 amperes per

microsecond at the package center. But the figure also reveals something interesting:

large values (≥ 20 amperes per microsecond) are distributed all across the package

area. Once again, the DUT package is reasonably efficient at spreading the current

load across the package area: the central “hot spot” is not all that hot.

Recall that in Section 5.1.2 we calculated that the test sockets added 1.3 nH of

inductance for adjacent VDD/VSS pin pairs. Using a

value of 20 amperes per

I∂

∂

microsecond, the voltage disturbance introduced by the socket is 26 mV, or 2.6

percent of the total supply voltage of 1 volt. This is a small enough number to justify

neglecting the disturbance of the sockets, but reducing this disturbance is a desirable

goal for future work.

| 22 A/uS 15 A/uS | | | — | — |

Figure 5.13. Values of VDD Pin

Figure 5.14. Distribution of Values of

I∂

∂

Estimates of

based on multiplying the worst case value by the number of

I∂

∂

VDD pins are sometimes used to be “conservative”. But this isn’t fair. First, as we’ve

seen, the VDD pin currents exhibit a range of values of

. If we simply add all of

I∂

∂

the currents into an aggregate current, the maximum rate of change of this current is

= 1.2 amperes per ns, whereas multiplying the maximum value by the number

I∂

∂

of pins (89) gives a value twice this large. Second, we’ve seen that bypass capacitors

connected to the vias of package pins are extremely effective at providing charge and

thus reducing the demand on the power plane. The correct approach is to apply the

distribution of current values and their rates of change to the printed circuit board in

simulation. This can be done directly if the requisite modeling information is available

from the IC vendor. Failing this, measurement data such as those presented here can

be used to reverse engineer a model for the packaged IC which can then be applied to

various printed circuit boards in simulation.

Lastly, we should confirm the validity of our assumption of quasi-static

conditions. This can be done by using an FFT to obtain the power spectrum of the

VDD current. Figure 5.15 shows the spectrum obtained for the aggregate VDD pin

current. It is evident that the vast majority of spectral power lies below 100 MHz.

There is a small amount of energy at multiples of 500 MHz, the DUT clock frequency,

but the spectrum is effectively band limited at 100 MHz. In the FR4 material used for

the printed circuit board, the phase shift across the package diagonal is 11%

of a

wavelength at 500 MHz. This confirms the validity of assuming quasi-static

conditions. This result also typifies a well designed die/package/board power system.

At each stage of the system, local charge storage in conjunction with equivalent series

resistance or inductance forms a low pass network that filters out high frequency

events. Well designed on-die and package power networks will prevent very high

frequency power currents from reaching the board, and local charge storage on the

board in turn prevents high frequency currents from reaching the power supplies.

Figure 5.15. Power Spectrum of Aggregate VDD Current

5.3 Sum

ary

This chapter has demonstrated a method for determining the transient current as a

function of time for each supply and ground package pin of ball grid array (BGA)

integrated circuit packages. Using an inductive loop, the voltage induced by the

transient currents is measured at each of the vias connecting the package pins to the

underlying printed circuit board. Once the matrix of mutual inductances between the

vias and measurement sites is known, matrix algebra and numerical integration can be

used to uniquely determine each pin’s current as a function of time. If, as was the case

in this application, the power spectrum of the power and ground currents contains

minimal energy above 500 MHz, quasi-static conditions can be assumed for packages

up to 2.5 cm on a side, and the mutual inductance matrix can be easily calculated

using the one-over-distance fall-off of magnetic field strength.

In the application presented, the device under test was a content addressable

memory having a 1 volt core supply voltage. Using alternating sequences of

consecutive matches and misses, abrupt current transitions of 8+ amperes were

created. Collectively, the current data gave some useful insights into the behavior of

the power network in the underlying printed circuit board. It was seen that while the

VDD and VSS current density is higher near the center of the package, three times as

much total current was carried by peripheral pins. We also saw that bypass capacitors

placed behind the part, on the backside of the board, are extremely effective in

supplying charge. When connected directly to a pin via, these bypass capacitors

supplied 80 to 120 percent of the pin’s current during transients. This tight bounding

indicates that there is limited current sharing to adjacent pins without attached bypass

for VDD currents showed a distribution across the area

capacitors. The values of

I∂

∂

of the package. The value of

for the measured aggregate VDD current was half

I∂

∂

the value that would be obtained by extrapolation from the pin with the highest value,

indicating the need for proper power system modeling. The measurement results could

certainly be used to verify the predictions of such power system modeling. The results

could also be used to generate a functional model of an integrated circuit’s power

current behavior if a first principles model is unavailable.

Figure 5.16. Distribution of VDD Pin Currents

(Pin A1 is at 0,0)

Figure 5.17. Distribution of VSS Pin Currents

(Pin A1 is at 0,0)

Figure 5.18. Distribution of Bypass Capacitor Currents

(Pin A1 is at 0,0)

Figure 5.19. Distribution of Power Plane Currents

(Pin A1 is at 0,0)

Chapter 6

Conclusion

This work has shown that fine-grained measurements of dynamic supply currents

can be made using the magnetic fields generated by these currents. Both the design

analysis of Chapter 3 and the results of the proof of concept tests discussed in Chapter

4 showed that inductive loop sensors can be inserted into industry standard printed

circuit boards and have an upper frequency limit of 2 GHz. Furthermore, our supply

current measurements in high performance printed circuit boards had an accuracy of

about 10%

. For repetitive signals, where averaging can be used, currents with a rate of

change as small as 6 µA/ns can be recovered with a signal to noise ratio better than 20

dB. In Chapter 5, the method was applied to a real problem and yielded valuable data

on power delivery.

Measurement of all power and ground package pin currents of a large CAM

memory showed that, as system designers have long suspected, there is non-

uniformity in the distribution of both the intensity and the rate of change of supply

current across the IC package. The VDD current density was found to be 33%

higher

at the center of the package versus the package periphery. Likewise, the highest time

rates of change of VDD currents were found in pins at the center of the package. The

degree of asymmetry, however, was less than expected. While VDD current density

was highest at the package center, three-fourths of the total current was carried by pins

outside of this area, and the time rate of change of VDD current in many peripheral

pins was two-thirds of the highest values at the package center. These results force the

conclusion that, at least for the case studied, transient current events are spread far

more evenly across the package pin area than is usually believed.

The effectiveness of bypass capacitors in supplying charge for current transients

was clearly seen. During current transients lasting up to 10 ns, capacitors placed on the

back of the board directly under a pin supplied 80 to 120 percent of the pin current.

This was true for both pins at the center of the package and those on the periphery.

Furthermore, only four out of twenty such capacitors supplied more than 120 percent

of the pin’s current, indicating that they were supplying neighboring pins. In contrast,

capacitors placed outside the package footprint and connected to the pin by a wide,

low impedance trace, supplied an average of only 50 percent the pin’s current. The

clear implication is that for transient current, the preferred supply path is along the z

axis, directly through the board. Designers should not assume that bypass capacitors

will effectively supply high current transients to multiple pins.

6.1 Directions for Future W

ork

In order to produce a practical instrument, the inductive probe should be

redesigned so that it is more robust. The planar loop used is far too mechanically

fragile to be practical for industrial use. Extremely precise alignment to the

measurement site is required to avoid breaking the probe tip. It is also difficult to

determine the exact depth of insertion. The point at which the end of the loop just

enters the printed circuit board must be found by observation, and the resulting

uncertainty can lead to measurement inaccuracies. Both of these problems can be

solved by using a cylinder in place of a plane as the loop armature, as shown in Figure

6.1. A 450 µm diameter rod of stable, non-conductive material with a relative

dielectric constant of three to four (such as a mineral filled plastic) forms the probe

armature. A slot for a #40 AWG wire is laser cut down the sides and around the end of

the rod, and the loop wire is cemented in the groove. The ends are attached to an SMA

connector (not shown) which is secured to the rod. A chamfer on the rod end eases

insertion, and a stop collar placed a known distance from the end of the rod ensures

precise and repeatable depth of insertion. These improvements would also reduce the

time required to make a set of measurements.

Figure 6.1. Cylindrical Loop Armature

With these improvements, a series of correlation studies could be undertaken

which compare simulations against measurements. Such studies would help to

determine if the simplifying assumptions typically used are appropriate. Actually

doing this, however, is complicated by the fact that simulation tools intended to be

applied to the Die/package/PCB system require a fairly detailed description of the die,

and IC vendors are often reluctant to disclose this information. Using the current

measurement method developed in this work, vendors of integrated circuits can

develop and verify models of the supply current networks of their parts. Behavioral

models could then be given to system designers to enable power system design. The

results discussed in Chapter 5 show that the distribution of current transients has major

implications for the design of printed circuit power networks, so system designers

should now require such models from IC vendors. It is possible, of course, to use this

current measurement method to develop ad hoc models for packaged integrated

circuits, and then use these models for printed circuit board design. But a better

approach is for the IC and system design communities to collaboratively develop a

sound modeling methodology which both protects intellectual property and facilitates

sound overall design.

We could imagine the possibility of embedding measurement loops in test sockets

and/or interposers to allow power current measurements for large integrated circuits

such as microprocessors. Also, with the on-going development of micro-vias and high

density interconnect for printed circuit boards, loops might be embedded directly into

the printed circuit board. It is also possible that they could be embedded in the IC

package itself, provided an adequate means for connecting them to measurement

circuits can be found. An array of such loops would allow the power usage of a system

to be monitored dynamically. The data might then be used to control activity so as to

optimize power delivery. Additionally, since this measurement approach is not limited

to power system currents, such embedded loops could be useful for non-contact

continuity testing. Critical signal traces between BGA packages can be difficult to

access, and at-speed testing is not possible with standard “bed of nails” testers.

Embedded loops would provide both signal access and at-speed measurements.

Finally, other sensor technologies might be applied to current measurement. Thin

film sensors based on induction loops with ferromagnetic cores (e.g. Permalloy) would

have higher inherent sensitivity, in trade for lower bandwidth, and small thickness.

This might allow insertion directly under BGA packages with extended solder ball

height. The printed circuit board areas around the perimeter of large packages is often

obstructed by other components, so this approach is not without its problems, but it

would eliminate the need for drilling the invasive non-plated hole required by the

present approach. Sensors based on Hall Effect devices, giant magneto-resistance or

magnetic tunnel junctions would allow sensing of DC and very low frequency (less

than 1 MHz) currents. While these devices may not be able to reach 1 GHz

frequencies, their use in conjunction with inductive loops would provide a DC to 2

GHz measurement range. By combining low and high frequency measurements, the

total power dissipation could be measured for an individual part. This would be of

great value to system designers, who usually have to rely on estimates from IC

designers and global measurements covering multiple integrated circuits.

6.2 Final Thoughts

Assuring the adequacy and cost effectiveness of power delivery networks is one of

the major challenges facing the designers of modern digital systems. If these networks

cannot supply sufficiently large dynamic currents, the performance of integrated

circuits is compromised, and the performance potential of modern CMOS circuits

cannot be achieved. A 6 GHz microprocessor is pointless if its operating frequency

must be kept to 2 GHz to achieve the required supply voltage stability. Yet designers

often do not have the resources to fully analyze power delivery networks.

Furthermore, designers have traditionally been restricted to supply voltage and

average power supply current measurements as their only diagnostic resources. This

has severely restricted their insight into power network behavior. Though not

glamorous, the continued development of current metrology will give designers the

ability to diagnose the sources of failure in power delivery systems as well as the

insight required to make these systems correct by design.

Appendix A

CAM

Test Board

The test board used to make the tests described in Chapter 5 was designed to

provide an electrical environment that resembled that of boards in which the CAM

memory would typically be used. The PCB contained eight stripline layers, six ground

plane layers for the striplines and four power/ground plane pairs. Two of these pairs

were located at the center of the board, while a pair was located near the top and also

the bottom of the board. The VDD/VSS plane pair for the CAM core supply was the

uppermost (towards the top surface of the board) of the two power ground pairs at the

board center. This placed core VDD/VSS pair approximately 20 µm off the board’s

center. Total board thickness was 3 mm, and FR4 dielectric was used throughout.

The completed test board is shown in top view in Figure A.1 below. To give some

positional stability, the board was inserted into the chassis of a commercial Ethernet

router. The chassis also supplied primary power to the on-board DC-DC converters,

which can be seen at the center of the bottom edge of the board. The four

SK0576BG2701A compression sockets, labeled U1 through U4, for placing the DUT

are clearly visible. The compression lids of the sockets have been removed for visual

clarity. SMA connectors mounted directly on the board allowed direct attachment to a

Tektronix TDS7704B oscilloscope for monitoring the system clocks as well as the

data acquisition trigger emitted by the controlling FPGA.

Figure A.1 – TCAM Test Board

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第二部分：模块化解读（中文 · DeepSeek 解读）

以下为对全文的模块化中文解读，非翻译，忠于英文原文。原文见第一部分。

〇、论文概览

一句话主题

本文提出一种通过测量磁场来在封装与PCB（印刷电路板）接口处测量瞬态电源电流的新方法，并验证了其带宽、灵敏度及在真实系统中的实用性。

研究背景与动机

CMOS集成电路的性能发挥依赖于电源网络提供足够的瞬态和稳态电流，以保证片上供电电压在指定范围内。随着MOS晶体管尺寸缩小，供电电压降低而电路密度增加，总功耗未减甚至上升，导致电源电流及其变化率大幅增加，电源网络设计愈发困难。测量电源网络中的电压和电流是开发良好设计/仿真实践、诊断实际系统问题的必要前提。

核心研究问题

如何实现封装到PCB接口处的瞬态电源电流测量？具体包括：能否用简单感应环做到足够小的尺寸（测量1 mm间距的PCB过孔）、足够的带宽（2 GHz）以及足够的灵敏度（检测小至6 µA/ns的重复电流变化），并应用于真实大规模集成电路的电源网络行为研究？

方法与技术路线（概述）

利用电流产生磁场的物理原理，采用简单的感应环（induction loop）作为磁场传感器。
通过感应环测量载流导体（如PCB过孔）周围的磁场，间接获取电流信息。
实验验证感应环的尺寸、带宽和灵敏度指标。
将方法应用于实际大规模集成电路的电源网络行为测量与分析。

主要贡献

提出一种在封装-PCB接口处测量瞬态电源电流的新方法，基于磁场感应原理。
证明感应环可小型化至测量1 mm间距PCB过孔的尺寸，具备2 GHz测量带宽。
证明该方法可检测小至6 µA/ns的重复电流变化，灵敏度足以捕捉真实PCB中的电源电流波动。
将方法成功应用于大规模集成电路电源网络行为的实验研究，验证其实用性。

论文结构（各章讲什么）

第1章引言：阐述研究背景、动机、问题定义及论文贡献概述。
第2章相关背景：回顾电源网络设计挑战、现有电流测量技术及其局限性。
第3章测量原理与方法：详细描述磁场感应测量原理、感应环设计、信号处理与校准方法。
第4章实验验证：展示感应环的尺寸、带宽、灵敏度等性能指标的实验测试结果。
第5章应用案例：将所提方法应用于真实大规模集成电路的电源网络行为测量，分析结果。
第6章结论与展望：总结研究成果，讨论方法的局限性与未来改进方向。

第1章引言（Introduction）解读

本章主旨

本章是全文的引言，旨在交代研究背景、问题动机、研究目标与论文结构。作者从硅工艺进步带来的性能提升入手，指出随之而来的功耗与供电网络设计挑战，进而引出本文的核心贡献——一种基于磁场测量的动态电流测量方法，并概述各章内容安排。

关键概念与术语（中英对照，挑重要的）

MOS晶体管（MOS transistors）：金属氧化物半导体场效应晶体管，是集成电路的基本器件。
栅极长度（drawn channel length）：晶体管沟道长度，是衡量工艺节点的重要参数。
ASIC（Application Specific Circuit）：专用集成电路，面向特定应用定制设计的芯片。
动态功耗（dynamic power dissipation）：电路开关活动引起的功耗，是供电网络设计的关键考量。
供电网络（power delivery network）：从电源到芯片内部电路的电能传输路径，包括封装、PCB等环节。
球栅阵列封装（ball grid array package）：一种表面贴装封装形式，通过焊球实现芯片与PCB的电气连接。
磁场（magnetic field）：电流周围产生的磁场，本文利用其测量电流。
测量带宽（measurement bandwidth）：测量系统能够准确响应的频率范围。

方法 / 论证要点（按原文逻辑拆解）

技术进步的正面效应：过去二十年硅工艺大幅进步，栅极长度从1 µm缩小至65 nm（45 nm在研），缺陷密度降低使1.5 cm²芯片可商用，集成度与时钟频率（从数十MHz到数GHz）均大幅提升，催生了新的数字逻辑应用。
技术进步带来的负面挑战：高集成度导致片上系统复杂度剧增；大芯片与先进工艺推高了流片成本（一套ASIC掩膜版耗资数百万美元）；而上市时间要求并未放宽，因此必须“一次设计正确”。
工具缺口：电路与系统仿真验证已有长足进展，但动态功耗估算工具发展滞后，导致设计者无法确保供电网络设计充分，只能过度设计（over-design），这阻碍了工艺进步的充分受益。
解决方案需求：开发动态功耗估算工具需要实验测量数据（电压与电流）作为验证依据。本文提出一种通过测量电流产生的磁场来测量供电网络中动态电流的方法。
方法定位与验证：演示地点选在球栅阵列封装与PCB之间的供电连接处，但方法具有通用性。初步结果显示：测量带宽可达2 GHz，误差约10%。
论文结构安排：第2章详述供电系统设计难点与测量需求；第3章进行设计可行性分析（磁场行为、设计方程、测量极限）；第4章给出探索性测量结果；第5章将方法应用于CAM存储器的动态供电电流实测；第6章讨论技术未来发展方向。

重要图表说明

无（本章为引言，未包含图表）。

本章与全文的关系 / 承上启下

本章作为论文的起点，完成了三重任务：一是建立研究背景，说明硅工艺进步带来的机遇与挑战；二是明确问题缺口——动态功耗估算工具缺失，进而引出对实验测量数据的需求；三是预告全文的技术路线与章节安排。通过将问题定位在“供电网络设计验证”这一具体工程需求上，本章为后续第2章的难点分析、第3章的可行性论证、第4章的实验验证以及第5章的实际应用铺设了逻辑链条，使读者对全文的技术动机和推进路径有清晰的预期。

第2章背景与相关技术（Background）解读

好的，遵照您的要求，我将对这篇博士论文的第2章进行模块化中文解读。

本章主旨

本章作为论文的“背景与相关技术”章节，系统地建立了研究问题域。作者首先剖析了现代集成电路供电系统（Power Delivery System）的物理结构与挑战，指出随着工艺缩放，供电已成为一个复杂难题。随后，本章论证了电源完整性（Power Integrity）的重要性，并介绍了用于验证电源网络性能的仿真与测量方法。最后，在指出现有电压测量方法局限性的基础上，作者提出了一种基于电感环（Inductive Loop）的新型电流测量方法，作为解决电源网络调试难题的关键，为后续章节（第3章）的深入研究奠定了理论基础和技术动机。

关键概念与术语（中英对照）

电源输送系统 (Power Delivery System, PDS)：从PCB板级电源到芯片内部，为集成电路供电的完整路径和网络。
电源完整性 (Power Integrity, PI)：确保电源网络在芯片工作期间提供稳定、高质量电压的能力。
片上供电网络 (On-die Power Distribution Network)：芯片裸片（Die）内部用于分配电源和地信号的金属网络。
封装电感 (Package Inductance)：由IC封装内电源和地网络物理分离产生的寄生电感，是造成电源噪声的主要因素。
IR压降 (IR Drop)：电流流过电源网络中的电阻（尤其是片上电阻）所产生的电压降。
旁路电容 (Bypass Capacitor)：放置在电源和地网络之间，用于在芯片电流需求突变时提供瞬时电荷，从而抑制电压波动的电容。
电源噪声 (Supply Noise)：电源电压相对于其理想值的波动，主要由IR压降和di/dt效应（电流变化率与电感的乘积）引起。
模型降阶 (Model Order Reduction)：一种数学方法，用于简化复杂线性网络的模型，在保证一定精度的前提下，去除对响应影响不大的高阶项，从而加快仿真速度。
片上测量 (On-die Measurement)：直接在芯片裸片上制作测试电路，用于测量内部节点的电压或电流信号。
电感环 (Inductive Loop)：一种基于电磁感应原理的电流传感器，通过测量导体周围磁场的变化来间接测量电流。

方法 / 论证要点（按原文逻辑拆解）

问题提出与系统描述：作者首先指出，技术缩放虽然提升了芯片性能，但也使得供电任务变得困难。接着，他详细描述了供电系统的组成（图2.1），包括PCB板级电源层、封装、片上网络，并逐一分析了各级的主要阻抗特性（片上电阻、封装电感、PCB传输线）及其对电压噪声的影响。
挑战加剧的根源：作者通过数据（图2.2）论证了问题的严重性。工艺缩放导致晶体管密度和开关速度大幅提升，使得电源电压降低（如1V）而总电流和电流变化率（di/dt）急剧增大（如80A以上，di/dt达1×10^8 A/s）。这直接导致对低阻抗（尤其是低电感）供电网络的需求，从而推动了封装技术（图2.3）和PCB设计（图2.4）的演进。
电源完整性的重要性：本节论证了为什么必须严格控制电源噪声。作者通过一个CMOS反相器模型（图2.5）推导出传播延迟与电源电压的近似关系（公式2.2），指出电源噪声会导致时序不确定性，进而降低系统性能。因此，高性能系统对电压容差有严格要求（如±5%），而模拟电路的要求则更为苛刻。
仿真验证的必要性与困境：为了在设计阶段确保电源完整性，必须依赖仿真工具。然而，作者指出了核心矛盾：非线性CMOS电路需用时域仿真器（如Spice），而庞大的线性互连网络则更适合用快速线性求解器或频域分析。直接对整个系统进行Spice仿真在计算上不可行。
仿真简化及其风险：为解决仿真困境，作者介绍了两种主要简化方法：分区仿真（将电路和互连分开模拟）和导频电路法（用少量真实电路控制大量电流源）。此外，还提到了模型降阶技术。但作者紧接着强调了这些简化可能引入的误差，如迭代不收敛、模型不稳定，尤其是非因果性（Non-causality） 问题，这些都会导致仿真结果不准确。
从仿真到测量：鉴于仿真存在不确定性，必须通过实际测量来验证。作者回顾了传统的封装引脚电压测量法，指出其在面对大芯片、高频率时已不适用，因此需要片上电压测量技术。他列举了多种片上测量方案（如电阻分压、比较器、示波器采样头、自相关提取等），并指出这些方法能提供有价值的验证数据。
提出新方法：电流测量：作者论证了仅测量电压的不足，指出电流信息对于定位仿真误差、计算实际网络阻抗至关重要。他提出，测量封装引脚处的瞬态电流，并结合片上电压测量，可以直接获得传输阻抗。为此，他提出使用单匝电感环作为电流传感器，并详细阐述了其优势：尺寸小、带宽高、噪声低、对被测电路影响小。最后，他描述了该传感器在PCB上的具体布置方案（图2.6），并讨论了其局限性（无法测直流、存在磁串扰）及应对方法。

重要图表说明

Figure 2.1 (Typical Power Supply Network)：展示了IC、封装、PCB和电源的完整连接示意图及其简化电路模型。该图旨在说明电流从电源出发，流经PCB、封装、片上网络，最终回到电源的路径，并强调各级网络（片上电阻、封装电感、PCB平面）在电气特性上的差异。
Figure 2.2 (Supply Voltage and Current Trends of High Performance Processors)：展示了25年来高性能处理器在特征尺寸、电源电压和功耗方面的趋势。该图旨在用数据说明，工艺缩放导致功耗和电流激增，而电压下降，从而加剧了供电设计的难度。
Figure 2.3 (IC Package Evolution)：展示了从传统PQFP封装到现代BGA封装的演进过程。该图旨在说明封装设计如何通过缩短VDD/VSS电流回路面积（从四周引脚到阵列引脚）来降低封装电感。
Figure 2.4 (PCB Cross-section under BGA Package)：展示了现代PCB在BGA封装下方的横截面结构，包括电源/地平面、过孔和旁路电容的布置。该图旨在说明如何通过紧耦合的平面层和靠近封装的电容来最小化回路电感和电源阻抗。
Figure 2.5 (CMOS Inverters)：展示了一个CMOS反相器驱动另一个反相器的电路图。该图用于推导门延迟与电源电压的关系，是论证电源噪声影响电路性能的基础。
Figure 2.6 (Inductive Loop Location)：展示了电感环传感器在PCB中的具体放置位置，即位于VDD和VSS过孔对之间的非电镀孔中。该图旨在说明如何利用该传感器测量流过特定过孔对的瞬态电流。

本章与全文的关系 / 承上启下

承上：本章建立在第1章（绪论）提出的“电源供电困难”这一核心问题之上，并对其进行了详细的技术背景展开。它没有直接给出解决方案，而是全面梳理了问题的成因、影响、现有解决手段及其不足。
启下：本章末尾明确指出现有电压测量方法的不足，并提出了“电感环电流测量”这一新思路，但仅停留在概念和初步可行性分析上。这为第3章（很可能是“提出的电流测量方法”的详细设计、理论分析、实现和验证）提供了直接的研究动机和清晰的技术路线。本章所描述的供电系统模型、仿真挑战和测量需求，构成了后续所有研究工作的基础和验证平台。

第3章测量方法与技术（Measurement Technique）解读

好的，遵照您的要求，我将对这篇博士论文的第3章进行模块化中文解读。

本章主旨

本章的核心目标是确立一种基于“单匝感应环”（single turn inductive loop）的PCB（印刷电路板）过孔（via）电流测量技术的理论基础与工程设计可行性。作者通过理论推导、数值分析和工程考量，系统地回答了三个关键问题：如何从理论上描述过孔电流产生的磁场并计算感应环的输出电压；如何设计一个在物理上可实现且性能可靠的感应环；以及这种测量方法在灵敏度和带宽方面的极限，以及它对被测电路本身可能产生的影响。

关键概念与术语（中英对照）

单匝感应环 (Single Turn Inductive Loop)：用于感应磁场变化的基本测量元件，其输出电压与穿过环路的磁通量变化率成正比。
过孔 (Via)：PCB中用于连接不同层之间电气连接的导电通路。
法拉第定律 (Faraday’s Law)：描述时变磁场如何在导体回路中感应出电动势的基本物理定律。
麦克斯韦方程组 (Maxwell’s Equations)：描述电磁场基本规律的一组方程，是本章理论分析的出发点。
趋肤深度 (Skin Depth, δS)：交流电磁场在导体中衰减至表面值的1/e时所穿透的深度。本章利用该概念论证了在大多数频率下，可以将PCB的电源/地平面视为理想导体。
互感 (Mutual Inductance, M)：描述一个电路中的电流变化在另一个电路中感应出电压的能力。本章推导了过孔与感应环之间的互感公式。
几何增益因子 (Geometrical Gain Factor)：一个无量纲参数，用于描述感应环的几何尺寸（宽度与间距之比）对输出电压的影响。
带宽 (Bandwidth)：测量系统能够有效工作的频率范围，本章主要关注上限频率。
自感 (Self Inductance, L)：导体自身电流变化在其周围产生磁链，从而在自身回路中感应出电压的特性。
空气芯变压器 (Air-core Transformer)：用于分析感应环（次级）与过孔对（初级）之间耦合效应的等效电路模型。

方法 / 论证要点（按原文逻辑拆解）

磁场建模（第3.1节）：
- 前提假设：首先，利用趋肤深度公式论证，在绝大多数感兴趣的频率下（>14 MHz），PCB内层的铜质平面远厚于趋肤深度，因此可以将过孔所在的电源/地平面近似为理想导体。这意味着电磁场被完全限制在平面层对之间，简化了分析模型。
- 理论推导：从麦克斯韦方程组出发，针对图3.1所示的过孔穿过平面层的结构，推导出载流过孔周围磁场的空间分布。核心结论是，磁场强度与电流成正比，且与距过孔中心的距离成反比。
感应环响应计算（第3.2节）：
- 电压公式推导：基于法拉第定律，计算一个位于过孔附近、具有特定宽度（W）和高度（h）的感应环所感应的电压。通过积分运算，得到了输出电压与过孔电流变化率、互感以及感应环几何位置的函数关系（公式3.1）。
- 互感公式：进一步推导出互感M(x, y)的解析表达式（公式3.2），该表达式是感应环中心相对于过孔位置的函数。
- 设计参数优化：引入无量纲参数δ（过孔间距D与环宽W之比），将输出电压公式简化为一个“几何增益因子”（公式3.3）。通过绘制该因子与δ的关系图（图3.4），发现增大环宽（即减小δ）可以增加增益。
- 容差分析：考虑到PCB制造公差会导致感应环位置偏移，作者分析了在x和y方向上的位移对输出电压的影响（公式3.4，图3.5，图3.6）。分析结果表明，选择δ=4（即W=D/4）是一个合理的折中方案，因为在此配置下，即使存在半个环宽的位移，输出电压的变化也小于10%，同时保持了可接受的增益（2.04）。
- 物理实现：基于上述分析，作者提出了一个具体的物理实现方案：使用标准PCB工艺，在FR4基板上制作一个76 µm宽、3 mm长的铜走线环，其总宽度（402 µm）可以适配在1 mm间距的BGA焊球之间，且所需的500 µm非镀通孔在工艺上是可行的。
测量极限分析（第3.3节）：
- 最小可检测信号：作者指出，感应环本身是一个极低阻值的电阻，其热噪声可忽略不计，因此系统的噪声基底主要由测量仪器（如Tektronix TDS7704B示波器）决定。根据该仪器的等效噪声电压（105 µVrms），结合计算出的互感值（M=613 pH），推算出在设定信噪比为1、电流幅值为10 mA的条件下，可测量的最低频率约为3.9 MHz，对应的最小电流变化率要求为0.75 mA/ns/mm。同时指出，通过多次平均可以降低噪声，从而放宽此限制。
- 测量带宽（上限频率）：将感应环和测量仪器的输入阻抗（50Ω）建模为一个简单的RL电路。分析其传递函数后发现，在低频段（低于转折频率），环路表现为微分器，需要积分才能恢复电流波形；在高频段，环路输出与电流成正比。为了简化信号处理并保证信噪比，希望转折频率高于1 GHz的目标测量上限。通过计算环路自感（L=3.2 nH），得出转折频率为2.5 GHz，满足设计要求。因此，测量方案确定为对感应环电压进行数值积分。
对被测电路的影响评估（第3.4节）：
- 对过孔阻抗的影响：将过孔对和感应环视为一个空气芯变压器（图3.8）。通过变压器方程推导出，电阻性端接的感应环会在过孔电路中引入一个与频率相关的负阻抗（公式3.7），即降低了过孔电路的有效电感，并增加了一个小的电阻分量。通过代入具体数值计算，在1 GHz频率下，电感相对减少约1%，增加的电阻约为原感抗的2%，结论是影响极小。
- 对电源/地平面阻抗的影响：为了评估为放置探针而钻的500 µm非镀通孔对电源/地平面阻抗的影响，作者使用商业场求解器（PowerSI®和PowerDC®）对有无该孔的两个测试结构（图3.9）进行了仿真。仿真结果显示，在10 MHz到1 GHz的频率范围内，该孔的存在对平面阻抗和直流电阻的影响是“难以察觉的”（imperceptible）。

重要图表说明

Figure 3.1：展示了分析模型的核心物理结构——一个载流过孔垂直穿过一对电源/地平面。该图定义了“区域A”（平面层对之间的空间），并说明了由于趋肤效应，电磁场被限制在该区域内。
Figure 3.2：展示了感应环与过孔的俯视几何关系。图中定义了感应环的中心位置（距离r，角度θ）、宽度W、高度h，以及过孔电流I_via，是推导互感公式的几何基础。
Figure 3.3：进一步明确了感应环中心位于过孔对连线中点（D/2, 0）的特殊情况，这是后续进行参数优化和容差分析的基准位置。
Figure 3.4：绘制了几何增益因子（V_out/V*）与参数δ（D/W）的关系曲线。该图直观地表明，δ值越小（即环越宽），增益越高，为选择环宽提供了理论依据。
Figure 3.5 & 3.6：分别展示了感应环在x方向和y方向发生位移（χ和ψ）时，输出电压相对于中心位置值的变化。图中不同曲线代表不同的δ值，用于评估制造公差的影响，并支持了选择δ=4作为最佳设计折中方案的结论。
Figure 3.7：展示了经过积分处理后的测量系统等效带宽响应曲线。该图说明了系统呈现“准低通”特性，即在高频段响应平坦，但无法测量直流信号，这是由最小可检测信号要求决定的。
Figure 3.8：将过孔对和感应环等效为空气芯变压器电路模型。图中标注了电压、电流方向以及自感（L1, L2）和互感（M），是分析测量探针负载效应对被测电路影响的理论基础。
Figure 3.9：展示了用于仿真研究的两个PCB测试结构。两个结构都包含过孔和反焊盘，区别在于第二个结构额外包含了一个用于放置探针的孔的反焊盘。该图用于评估探针孔对电源/地平面阻抗的影响。

本章与全文的关系 / 承上启下

本章是论文的核心方法论章节，起到了承上启下的关键作用。

承上：它承接了第2章（或引言）中提出的研究问题——即需要一种能够精确测量PCB内部过孔电流的技术。本章通过严谨的电磁场理论和电路分析，为这一需求提供了具体的、可工程实现的解决方案。
启下：本章通过理论推导和仿真验证，确立了测量技术的可行性、设计参数和性能边界。这为后续章节（如第4章及以后）的实验验证、原型制作、实际测量以及可能的数据处理和分析方法奠定了坚实的理论基础和设计蓝图。本章得出的具体设计参数（如环宽W=D/4，环高h=3mm）和测量策略（如对电压进行积分）将直接指导后续的实践工作。

第4章探索性测量与验证（Exploratory Measurements）解读

好的，这是对您提供的博士论文第4章的模块化中文解读：

本章主旨

本章的核心目标是通过实验验证前一章提出的理论设计——即利用小型感应环（induction loop）作为传感器，来测量印刷电路板（PCB）中过孔（via）内流过的交流电流。作者设计并执行了两组独立的实验，旨在证明该测量方法的可行性、准确性以及在实际复杂环境（如真实路由器主板）中的适用性。实验不仅验证了理论预测的磁场衰减规律，还确定了传感器的测量带宽和灵敏度极限，为后续章节中利用该技术进行更深入的研究奠定了坚实的实验基础。

关键概念与术语（中英对照）

感应环 (Induction Loop)：一个单匝或多匝的导线环，用于通过磁感应原理探测导体中的电流变化。
过孔 (Via)：印刷电路板上用于连接不同层之间导线的镀铜孔。
互电感 (Mutual Inductance)：一个电路中的电流变化在另一个电路中感应出电压的能力。在本章中，它是连接过孔电流与感应环输出电压的关键参数。
断裂频率 (Break Frequency)：传感器（感应环）的频率响应上限，由环的自感和终端阻抗决定（f = R/L）。在此频率之上，输出电压不再与电流变化率（di/dt）成正比。
SSTL2 (Stub Series Terminated Logic 2)：一种用于DDR内存等高速数字接口的I/O标准，其输出具有特定的电压摆幅和终止方案。
BGA封装 (Ball Grid Array)：一种集成电路的表面贴装封装形式，其引脚为芯片底部的球形焊点阵列。
电磁干扰 (EMI)：电磁干扰，指电子设备产生的、可能干扰其他设备正常工作的电磁辐射。
矢量网络分析仪 (VNA)：用于测量电子网络散射参数（如S21）的仪器，在本章中用于测量感应环的频率响应。
时域反射计 (TDR)：用于测量传输线或电路阻抗特性的仪器，在本章中用于交叉验证感应环的自感值。
准静态条件 (Quasi-static Conditions)：当电路尺寸远小于工作波长时，可以忽略电磁波的传播效应，用静态场理论近似分析的条件。

方法 / 论证要点

本章通过两个递进的实验来构建论证：

第一项测试：理想环境下的原理验证 (SSTL寄存器缓冲器)
- 目的：在“最佳情况”环境下，验证感应环测量过孔电流的基本物理原理。
- 方法：
  - 使用一个商用SSTL2缓冲器产生已知的电流模式，通过测量其端接电阻上的电压来确定电流的真实值，作为对比基准。
  - 设计了一个带有模拟BGA过孔阵列的测试夹具，允许插入一个1mm x 1mm的感应环。
  - 首先，通过VNA和TDR测量感应环的断裂频率（约2GHz），确认其满足1GHz的设计目标。
  - 其次，利用一个孤立的电流双极子（VDD/VSS过孔对）验证了磁场强度随距离成反比（1/d）的理论预测。
  - 最后，测量所有输出过孔的电流，并通过计算互电感矩阵来消除相邻过孔间的磁串扰，将测量结果与已知电流值进行对比。
- 结果与论证：实验成功验证了磁场衰减规律。在消除串扰后，大部分电流测量误差在10%以内，但存在约20%的系统性误差。作者分析指出，该误差源于芯片传统引线框架封装产生的EMI，并论证了现代BGA封装能有效避免此问题，从而证明了方法的有效性。
第二项测试：真实环境下的应用验证 (商用以太网路由器主板)
- 目的：证明该技术在实际、复杂的PCB环境中（如高端路由器）的可行性和实用性，并确定其实际灵敏度极限。
- 方法：
  - 设计了一种基于标准PCB工艺的平面感应环，其尺寸足够小，可以插入间距为1mm的BGA过孔之间。
  - 在一台真实的路由器主板上，于4个BGA封装下钻了80个测量孔位，并设计了一个校准位。
  - 通过校准位，确定了该探头的测量带宽（>2GHz）和最小可检测电流（通过信号平均，可检测到6µA/ns的重复信号）。
  - 在路由器运行真实以太网流量时，对80个位点进行了电流测量，并展示了内容寻址存储器（CAM）芯片的VDDQ和VDD引脚的电流特征。
  - 通过改变感应环的插入深度，验证了电源/地平面层对测量结果的影响可忽略不计，并探究了旁路电容的作用。
- 结果与论证：在真实环境中，所有80个位点均获得了清晰的测量信号。在磁串扰最小的位点，测量值与理论计算值（如132mA峰值电流）高度吻合（误差小于5%）。实验还成功观测到了与芯片活动相关的瞬态电流模式及其在封装上的分布。这些结果有力地证明了该测量技术在真实世界中的强大功能和实用性。

重要图表说明

Figure 4.1：第一项测试的电路原理图，展示了如何利用SSTL缓冲器、端接电阻和时钟配置来产生已知的电流模式。
Figure 4.2 & 4.3：第一项测试的机械结构图和实物照片，展示了如何构建一个带有模拟过孔阵列的测试夹具，并允许插入感应环。
Figure 4.4：1mm方形感应环的频率响应曲线，显示其断裂频率约为2GHz，验证了其测量带宽。
Figure 4.5：VDD/VSS过孔对（45/46）的感应环输出电压波形，两者互为镜像，表明电流大小相等、方向相反，形成了理想的电流双极子。
Figure 4.6：磁场强度随距离衰减的实测数据与理论曲线对比，验证了1/d的衰减规律。
Figure 4.7：输出引脚电流的测量值与真实值对比图，直观展示了测量的准确性（大部分误差<10%）。
Figure 4.8 & 4.9：VDDQ和VSSQ电源引脚的电流测量结果，通过电流守恒定律验证了测量的合理性。
Figure 4.10 & 4.11：第二项测试中平面感应环的设计图和插入PCB的示意图，展示了其微型化设计和实际应用方式。
Figure 4.12：平面感应环的频率响应，确认其同样具有超过2GHz的带宽。
Figure 4.13：校准位设计及恢复的电流信号，用于确定探头的灵敏度和最小可检测信号。
Figure 4.14 & 4.15：在真实路由器上测得的CAM芯片VDDQ和VDD引脚的电流特征，展示了实际应用效果。
Figure 4.16：CAM芯片封装上不同VDD引脚峰值电流的分布图，展示了测量技术用于分析芯片内部电流分布的能力。
Figure 4.17 & 4.18：感应环输出电压随插入深度变化的曲线，用于验证电源/地平面层对测量的影响，并确定平面层位置。
Figure 4.19：探究VDD旁路电容对测量信号影响的实验结果。

本章与全文的关系 / 承上启下

承上：本章是实验验证章节，直接回应了第3章的理论分析和设计预测。它用实验数据证实了第3章中关于磁场衰减、感应环断裂频率、互感计算以及灵敏度估算等核心理论，将理论模型转化为经过验证的工程工具。
启下：本章成功开发并验证了一种实用、可靠的过孔电流测量技术。这为后续章节（如第5章）利用该技术进行更深入的科学研究铺平了道路。例如，可以使用该技术来：
- 验证复杂的电路仿真模型。
- 研究电源分配网络（PDN）的真实行为。
- 分析芯片不同逻辑模块的功耗分布。
- 诊断和解决实际的电磁兼容（EMI）问题。因此，本章是连接理论分析与实际应用的关键桥梁，其结论和方法论是后续研究工作的基础。

第5章实际应用案例（Application to a Real Problem）解读

本章主旨

本章将前文发展的电感环传感器测量技术应用于一个真实工程问题：测量大型集成电路（CAM芯片）所有电源/地引脚上的瞬态电流分布。核心目标是验证该方法在实际场景中的可行性，并回答系统设计者关心的三个问题：电流在封装引脚场上的空间分布、旁路电容的实际有效性、以及到达PCB板的∂I/∂t最大值。通过实测数据，本章还检验了若干传统设计假设（如“热点”区域主导电流、旁路电容会均流等）是否成立。

关键概念与术语（中英对照）

中文	英文	说明
内容寻址存储器	Content Addressable Memory (CAM)	测试芯片，常用于以太网路由器
内置自测逻辑	Built-In Self Test (BIST)	芯片内部测试模式，无需外部输入控制
待测器件	Device Under Test (DUT)	被测的CAM芯片
准静态近似	Quasi-static approximation	忽略信号传播相位效应的简化假设
互电感矩阵	Mutual inductance matrix (M)	描述各测量点与各过孔间磁耦合的矩阵
旁路电容	Bypass capacitor	提供瞬态电荷的储能元件
电源/地平面	Power/ground plane pair	PCB中的平行板波导结构
磁场近场衰减	Near-field fall-off (1/d)	磁场强度随距离反比衰减
压缩插座	Compression socket	连接DUT与测试板的低电感插座
热区	“Hot spot”	封装中心下方预期电流密度最高的区域
电流变化率	∂I/∂t	电流对时间的导数，衡量瞬态电流的剧烈程度

方法 / 论证要点

1. 测试器件选择（5.1.1）

选择CAM的理由：CAM具有搜索模式，搜索不匹配时会产生大幅电流摆动，且内置BIST逻辑可自动执行测试模式，无需外部控制，简化了测试板设计。
BIST测试算法：交替执行连续匹配和连续不匹配的搜索序列，以制造最恶劣的∂I/∂t条件。
封装特征：576球BGA封装，1V核心电压，500MHz时钟，引脚分布显示中心区域VDD/VSS密度高（即“热点”），但大量信号引脚穿插其间。

2. 测试板设计（5.1.2）

关键设计策略：为每个过孔设置测量点会过度增加PCB孔隙率，因此采用四个相同布局但测量点位置错开的footprint，每个footprint含144个测量点，通过移动DUT到四个位置覆盖全部576个引脚。
环境真实性：层叠结构与实际以太网路由器板一致（24层，3mm厚），旁路电容的容值和布局也参照实际产品。
插座影响评估：压缩插座增加1.3nH电感，经计算对相邻VDD/VSS过孔对的干扰可容忍。

3. 测量方法（5.1.3）

时序同步：FPGA与DUT同步工作，通过触发脉冲确保四次测量数据的相干合并。
双深度测量法：每个测量点取两次读数——半插入（仅到核心电源平面）和全插入。相减得到引脚电流，半插入数据单独用于提取旁路电容电流，再通过组合运算得到平面电流。
准静态条件验证：电源/地平面构成平行板波导，传播模式为TEM，在FR4材料中2GHz下准静态距离极限为7.5mm。实测信号频谱能量基本低于100MHz，远满足准静态条件。
数据处理：利用互电感矩阵M和矩阵代数求解电流向量，数值积分采用梯形近似，MATLAB左除函数求解。

4. 磁场行为验证（5.2.1）

实测验证：在空白PCB上注入已知∂I/∂t信号，对比预测与实测感应电压，误差≤800µV。
仿真交叉验证：HFSS三维场求解器模拟有信号过孔和地过孔干扰的情况。结果显示信号过孔干扰很小，地过孔在低场强区域有一定扰动（可能源于低品质因数谐振），但整体误差可控。

5. 电流测量结果（5.2.2）

总体电流验证：所有VDD引脚电流之和约为12A方波脉冲，VDD与VSS电流之和（应为零）最大偏差仅5%，且与DC-DC转换器读出的平均电流（4.1A）吻合。
空间分布：中心区域每引脚平均电流比外围高30-33%，但外围引脚贡献了总电流的77%——说明封装在扩散电流负载方面表现良好。
旁路电容有效性：直接连接到引脚过孔的旁路电容在瞬态期间提供了该引脚电流的80-120%，说明电流共享非常有限——这否定了传统设计假设（相邻引脚会均流）。
∂I/∂t分布：最小值5A/µs，最大值30A/µs（封装中心），但≥20A/µs的值分布在整个封装区域。聚合总电流的∂I/∂t（1.2A/ns）仅为最大引脚值乘以引脚数（89）所得值的一半——说明简单外推会过度保守。

重要图表说明

图号	内容	说明
Figure 5.1	CAM封装引脚顶视图	显示VDD（红）和VSS（蓝）引脚分布，中心“热点”区域密度高
Figure 5.2	测试板框图	FPGA控制BIST、JTAG编程、时钟生成、触发输出
Figure 5.3	DUT footprint与过孔场	(a)焊盘布局；(b)过孔排列形成2mm宽的“通道”
Figure 5.4	旁路电容布局	0.1µF电容对角跨接VDD/地过孔，2.2µF IDC在边缘，100µF在角落
Figure 5.5	双深度测量示意	半插入与全插入两种环路位置
Figure 5.6	空白PCB测试位置	用于磁场衰减验证
Figure 5.7	HFSS仿真（信号过孔）	三个频率下磁场强度基本一致，与近场预测吻合
Figure 5.8	HFSS仿真（地过孔）	地过孔在低场强区引起扰动，可能有低Q谐振
Figure 5.9	总VDD和VSS电流	约12A方波脉冲，VDD+VSS之和最大偏差5%
Figure 5.10	平均每引脚VDD电流	中心vs外围对比，中心高30-33%
Figure 5.11	旁路电容电流贡献	有/无电容的相邻引脚对比，电容提供90%电流
Figure 5.12	旁路电容贡献比例3D图	80-120%范围，显示电流共享有限
Figure 5.13	引脚∂I/∂t值	中心引脚比角落引脚高50%
Figure 5.14	∂I/∂t分布3D图	5-30A/µs范围，大值分布在整个封装区域
Figure 5.15	聚合VDD电流功率谱	能量基本低于100MHz，验证准静态假设
Figures 5.16-5.19	多面板时序图	VDD引脚、VSS引脚、旁路电容、电源平面的电流空间分布随时间的演化

本章与全文的关系 / 承上启下

承上：本章是前四章理论与方法论的集成验证。第2章讨论了电源网络仿真的重要性，第3章建立了电感环传感器的理论基础（互感计算、带宽/灵敏度分析），第4章验证了传感器在PCB环境中的测量精度。本章将这些成果综合应用于一个真实的大规模IC电源引脚电流测量问题，证明了该技术的实用价值。

启下：本章的实测数据为第6章（后续章节）提供了基础——测量结果可用于验证电源网络仿真模型的准确性，也可在缺乏IC厂商模型时反向构建功能模型。本章揭示的“旁路电容电流共享有限”和“∂I/∂t分布不均匀”等发现，对PCB设计实践有直接指导意义。此外，作者在文中指出“地过孔对磁场的扰动”和“插座电感干扰”是未来可改进的方向，为后续研究留出了空间。

方法论意义：本章展示了一套完整的“从传感器设计→测试板构建→数据采集→信号处理→结果分析”的闭环流程，为将电感环测量技术推广到其他IC封装类型和电源网络场景提供了可复制的范式。

第6章结论（Conclusion）解读

本章主旨

本章作为博士论文的收束章节，首先总结了全文的核心贡献——证明利用电流产生的磁场可以对动态供电电流进行精细测量，并回顾了各章的关键成果：感应式环路传感器可嵌入工业标准PCB、上限频率达2 GHz、测量精度约10%、可恢复低至6 µA/ns的电流变化率。随后，本章将方法应用于实际CAM存储器问题，揭示了供电电流在IC封装引脚上分布的非均匀性，并验证了旁路电容在瞬态电流供应中的有效性。最后，作者从工程实用化、建模方法论、传感器技术演进三个维度提出了未来研究方向，并以对供电网络设计挑战的宏观思考作结。

关键概念与术语（中英对照）

英文术语	中文译名	简要说明
Dynamic supply currents	动态供电电流	集成电路运行时电源引脚上的瞬态电流
Inductive loop sensors	感应式环路传感器	利用电流产生磁场进行非接触式测量的传感器
Signal to noise ratio (SNR)	信噪比	衡量信号质量与噪声水平的比值
CAM memory	内容寻址存储器	一种特殊类型的存储器，用于高速搜索
VDD current density	VDD电流密度	电源电压引脚上单位面积的电流强度
Bypass capacitors	旁路电容	用于在瞬态期间提供电荷的电容
Package footprint	封装占位面积	IC封装在PCB上所占的物理区域
Z-axis supply path	Z轴供电路径	电流沿垂直方向直接穿过PCB板的路径
Behavioral models	行为模型	描述IC外部电气特性的简化模型
Interposers	中介层	连接IC封装与PCB的中间基板
Micro-vias	微过孔	高密度互连中使用的小尺寸过孔
BGA packages	球栅阵列封装	一种表面贴装封装形式
Bed of nails testers	针床测试仪	传统PCB测试设备
Permalloy	坡莫合金	一种高磁导率的铁镍合金
Hall Effect devices	霍尔效应器件	基于霍尔效应的磁场传感器
Giant magneto-resistance	巨磁阻效应	磁场引起电阻显著变化的现象
Magnetic tunnel junctions	磁隧道结	基于量子隧穿效应的磁场传感器

方法 / 论证要点

本章的论证逻辑遵循”总结—应用—展望”的三段式结构：

第一段：研究贡献的系统性回顾。 作者将第3章的传感器设计分析与第4章的概念验证测试结果并列，建立”设计—验证”的完整证据链。关键论证要点包括：传感器可嵌入工业标准PCB、频率上限达2 GHz、精度约10%、在可平均的重复信号条件下可恢复极小的电流变化率。第5章的实际应用则证明了该方法对真实问题的诊断价值。

第二段：核心实证发现的提炼与解读。 作者从CAM存储器测量中提炼出两个关键结论。其一，供电电流分布的非均匀性——VDD电流密度在封装中心比外围高33%，但整体不对称程度低于预期：四分之三的总电流由中心区域以外的引脚承载，许多外围引脚的时间变化率仍达中心最高值的三分之二。这一发现直接挑战了系统设计者长期以来的假设，表明瞬态电流事件在封装引脚区域的分布远比通常认为的均匀。其二，旁路电容的供电有效性——位于引脚正下方PCB背面的电容在瞬态期间提供了引脚电流的80%至120%，而封装占位面积之外通过宽低阻抗走线连接的电容平均仅提供50%。这一对比论证了瞬态电流的首选路径是沿Z轴直接穿过PCB板，而非通过水平走线。

第三段：未来研究方向的系统规划。 作者从四个层面展开：工程实用化（探针的机械鲁棒性改进，提出圆柱形线圈骨架方案）、建模方法论（仿真与测量的相关性研究、IC供应商与系统设计者的协作建模）、应用拓展（嵌入测试插座、中介层、PCB甚至IC封装中的测量环路阵列）、技术演进（基于铁磁芯薄膜传感器、霍尔效应、巨磁阻、磁隧道结等新型传感技术，实现DC至2 GHz的全频段覆盖）。

重要图表说明

Figure 6.1 – Cylindrical Loop Armature（圆柱形环路骨架）

该图展示了一种改进后的探针设计方案。图中呈现的是一根直径450 µm的稳定非导电材料圆棒（相对介电常数3至4，如矿物填充塑料），作为探针骨架。沿圆棒侧面和末端用激光切割出用于容纳#40 AWG导线的槽，导线粘固在槽内，两端连接至SMA连接器。圆棒末端设有倒角以便插入，距末端已知距离处设有止动环以确保插入深度精确可重复。该图旨在说明如何解决平面环路探针机械脆弱、对齐困难、插入深度不确定等工程问题，使探针更适用于工业环境。

本章与全文的关系 / 承上启下

本章作为博士论文的结论章，承担着三重功能。在收束层面，它系统性地整合了第3章（传感器设计分析）、第4章（概念验证测试）和第5章（实际应用研究）的核心成果，将分散的技术细节凝练为具有普遍意义的研究结论——供电电流分布的非均匀性程度低于预期、Z轴是瞬态电流的首选供应路径。在提升层面，本章将具体测量结果上升为对系统设计实践的指导性建议：设计者不应假设旁路电容能有效向多个引脚提供高瞬态电流，应要求IC供应商提供供电电流网络的行为模型。在开放层面，本章通过未来研究方向展示了该测量方法的广阔应用前景，从探针工程化改进到新型传感技术融合，从单点测量到阵列化动态监控，从电源电流测量到非接触连续性测试，勾勒出一条从实验室验证走向工业实用的清晰路径。最后的”Final Thoughts”将研究置于现代数字系统设计的宏观语境中，以”6 GHz微处理器若需降至2 GHz运行才能维持供电电压稳定则毫无意义”这一生动比喻，强调了电流计量学发展对实现CMOS电路性能潜力的战略意义。

附录 A（Appendix A：测试板文档）解读

本章主旨

本附录为博士论文的测试板文档，详细描述了用于第五章实验的CAM（内容可寻址存储器）测试板的物理设计与结构。其核心目的是说明测试板的电气环境设计——即如何模拟CAM存储器在实际应用场景中的工作条件，从而保证第五章实验数据的可信度与代表性。

关键概念与术语（中英对照，挑重要的）

CAM（Content-Addressable Memory）：内容可寻址存储器，论文的研究对象
Test Board：测试板，用于承载被测器件（DUT）并进行电气测试的PCB平台
Stripline：带状线，一种PCB内层传输线结构，用于信号布线
Ground Plane：接地平面，PCB中用于提供参考地电位的铜层
Power/Ground Plane Pair：电源/地平面配对层，用于为芯片提供稳定的供电回路
VDD/VSS Plane Pair：核心供电的电源/地平面配对，VDD为正电源，VSS为地
FR4：常见的PCB基板材料，玻璃纤维环氧树脂
Compression Socket：压缩式插座，用于无焊接方式安装被测芯片（DUT）
DUT（Device Under Test）：被测器件
SMA Connector：SMA同轴连接器，用于高频信号的外部接入
DC-DC Converter：直流-直流转换器，将外部电源转换为板上各供电轨所需电压
FPGA（Field-Programmable Gate Array）：现场可编程门阵列，用于控制测试流程与数据采集

方法 / 论证要点（按原文逻辑拆解）

本附录的论证逻辑围绕”测试板的电气设计如何保证实验有效性”展开，具体要点如下：

设计目标：测试板的设计目的是提供一个与CAM存储器实际使用场景相似的电气环境。这意味着测试结果不是理想化条件下的数据，而是贴近真实应用的表现。
层叠结构设计：PCB包含8个带状线信号层、6个带状线接地平面层，以及4个电源/地平面配对层。这一层叠配置为信号完整性提供了充足的参考平面和隔离。
电源/地平面布局：4个电源/地平面配对中，2对位于板中心，1对靠近板顶部，1对靠近板底部。CAM核心供电的VDD/VSS平面配对位于板中心两对中的最上层，距板中心约20µm。这一细节说明设计者关注核心供电的回流路径对称性。
物理参数：板总厚度3mm，全部使用FR4介质材料。FR4是标准工业材料，说明该测试板并非特殊定制的高端工艺，而是代表典型应用环境。
机械与系统集成：测试板被安装到商用以太网路由器的机箱中，以获得位置稳定性。机箱同时为板载DC-DC转换器提供初级电源。这一设计进一步强化了”真实使用环境”的模拟目标。
器件安装与观测：板上设有4个SK0576BG2701A压缩插座（编号U1~U4），用于放置被测器件。压缩式插座避免了焊接对芯片的损伤，也便于更换不同DUT。SMA连接器直接安装在板上，用于连接Tektronix TDS7704B示波器，监测系统时钟以及FPGA发出的数据采集触发信号。

重要图表说明

Figure A.1 – TCAM Test Board（TCAM测试板俯视图）

该图展示了完成后的测试板俯视外观。图中可见：板底部中央的DC-DC转换器、4个压缩插座（U1~U4，为清晰起见已移除压缩盖）、以及用于连接示波器的SMA连接器。该图的作用是让读者直观了解测试板的物理布局，与文字描述相互印证。

本章与全文的关系 / 承上启下

本附录是第五章实验的硬件基础说明。第五章描述了基于该测试板进行的CAM测试及其结果，而本附录提供了这些测试所依赖的物理平台细节。通过详细说明测试板的层叠结构、供电布局、器件安装方式和信号观测手段，本附录为读者评估第五章实验数据的有效性提供了必要的硬件背景。它回答了”测试在什么样的环境中进行”这一关键问题，从而支撑了实验结论的可信度。作为附录，它不打断正文的叙述流畅性，但为有需要的读者提供了深入的技术细节。

参考文献（Bibliography）解读

参考文献章节解读

本章主旨

本章为博士论文的参考文献列表，系统收录了论文所引用的全部学术文献，涵盖集成电路电源噪声测量、片上供电网络设计、封装技术、电磁兼容性、CMOS器件建模等多个研究领域。文献时间跨度从1967年至2006年，反映了该研究方向的学术脉络与前沿进展。

关键概念与术语（中英对照，挑重要的）

Bibliography — 参考文献
On-Chip Power Supply Noise — 片上电源噪声
Decoupling Capacitor — 去耦电容
Power/Ground Plane — 电源/地平面
Electromagnetic Compatibility (EMC) — 电磁兼容性
Flip-chip Package — 倒装芯片封装
Sampling Oscilloscope — 采样示波器
Signal Integrity — 信号完整性
Power Distribution System — 配电系统
Short-Channel MOS Devices — 短沟道MOS器件
Near-Field Magnetic Scanning — 近场磁扫描
Droop Detector — 电压跌落检测器
di/dt Detector — 电流变化率检测器
Resonance Damping — 谐振阻尼
Embedded Capacitance — 嵌入式电容

方法 / 论证要点（按原文逻辑拆解）

参考文献按第一作者姓氏字母顺序排列，采用IEEE引用格式，编号系统为[作者缩写+年份]。文献来源类型多样，主要包括以下几类：

期刊论文：来自IEEE Journal of Solid-State Circuits、IEEE Transactions on Advanced Packaging、IEEE Transactions on Electromagnetic Compatibility等权威期刊，如[ASH05]关于片上电源噪声高分辨率测量技术、[MTR04]关于片上电压跌落检测器等。
会议论文：来自IEEE International Solid-State Circuits Conference (ISSCC)、IEEE Symposium on VLSI Circuits、IEEE International Symposium on Electromagnetic Compatibility等顶级会议，如[TMN02]和[IDT06]分别介绍了不同采样率的片上采样示波器设计。
学术专著与教材：包括Gray等人的《Analysis and Design of Analog Integrated Circuits》、Taur和Ning的《Fundamentals of Modern VLSI Devices》等经典教材，为器件建模和电路分析提供理论基础。
学位论文：[Hor83]为Horowitz在Stanford University的博士论文，研究CMOS电路时序模型，是该领域的重要奠基性工作。
私人通信：[Wor89]标注为Wordeman与Taur和Ning的私人通信，被引用在Taur和Ning的专著中。

重要图表说明

无（本章为参考文献列表，不含图表）。

本章与全文的关系 / 承上启下

作为论文的收尾章节，参考文献列表完整呈现了论文所依托的学术资源，具有多重功能：其一，为正文中的各项技术主张提供可追溯的学术依据，增强论文的可信度与可验证性；其二，通过引用从1960年代经典电磁场理论（[RWV67]）到2000年代中期最新研究成果（如[HAP05]关于CMOS缩放与功耗的展望）的文献，勾勒出该研究领域近四十年的发展脉络；其三，文献覆盖电源完整性、信号完整性、封装设计、器件物理、测量技术等多个交叉学科方向，体现了该博士论文研究的跨学科特征与学术视野。参考文献的编排规范、来源权威，也从一个侧面反映了论文本身的学术严谨性。

半导体投资

PCB 电源完整性供电电流功率分配网络电流测量博士论文

本文由作者按照 CC BY 4.0 进行授权

第一部分：正文（Original Article / 英文原文）

第二部分：模块化解读（中文 · DeepSeek 解读）

〇、论文概览

一句话主题

研究背景与动机

核心研究问题

方法与技术路线（概述）

主要贡献

论文结构（各章讲什么）

第1章 引言（Introduction） 解读

本章主旨

关键概念与术语（中英对照，挑重要的）

方法 / 论证要点（按原文逻辑拆解）

重要图表说明

本章与全文的关系 / 承上启下

第2章 背景与相关技术（Background） 解读

本章主旨

关键概念与术语（中英对照）

方法 / 论证要点（按原文逻辑拆解）

重要图表说明

本章与全文的关系 / 承上启下

第3章 测量方法与技术（Measurement Technique） 解读

本章主旨

关键概念与术语（中英对照）

方法 / 论证要点（按原文逻辑拆解）

重要图表说明

本章与全文的关系 / 承上启下

第4章 探索性测量与验证（Exploratory Measurements） 解读

本章主旨

关键概念与术语（中英对照）

方法 / 论证要点

重要图表说明

本章与全文的关系 / 承上启下

第5章 实际应用案例（Application to a Real Problem） 解读

本章主旨

关键概念与术语（中英对照）

方法 / 论证要点

1. 测试器件选择（5.1.1）

2. 测试板设计（5.1.2）

3. 测量方法（5.1.3）

4. 磁场行为验证（5.2.1）

5. 电流测量结果（5.2.2）

重要图表说明

本章与全文的关系 / 承上启下

第6章 结论（Conclusion） 解读

本章主旨

关键概念与术语（中英对照）

方法 / 论证要点

重要图表说明

本章与全文的关系 / 承上启下

附录 A（Appendix A：测试板文档） 解读

本章主旨

关键概念与术语（中英对照，挑重要的）

方法 / 论证要点（按原文逻辑拆解）

重要图表说明

本章与全文的关系 / 承上启下

参考文献（Bibliography） 解读

参考文献章节解读

本章主旨

关键概念与术语（中英对照，挑重要的）

方法 / 论证要点（按原文逻辑拆解）

重要图表说明

本章与全文的关系 / 承上启下

热门标签

第1章引言（Introduction）解读

第2章背景与相关技术（Background）解读

第3章测量方法与技术（Measurement Technique）解读

第4章探索性测量与验证（Exploratory Measurements）解读

第5章实际应用案例（Application to a Real Problem）解读

第6章结论（Conclusion）解读

附录 A（Appendix A：测试板文档）解读

参考文献（Bibliography）解读