半导体 21
- AI and Amoeba, Fighting Together — Learning intelligence and mediating intelligence — AI 与变形虫并肩作战：学习智能与中介智能
- Advanced Packaging Co-Design: The Thermodynamic and Mechanical Constraints of High Power GPUs — 先进封装协同设计：高功耗 GPU 的热力学与力学约束
- CPO's Biggest Bottleneck Is Not Optics—It Is High-Volume Testing — CPO 的最大瓶颈不是光学，是量产测试
- AMD and Cerebras Announce Industry-Leading Ultra-Low-Latency and High Throughput AI Inference Solution — AMD 与 Cerebras 推出行业领先的超低延迟、高吞吐 AI 推理方案
- July NPO/CPO Update: Stupidity Singularity — NPO/CPO 七月更新：激光护城河、VCSEL CPO 与 Nvidia 供应链变局
- The Inference Chip Architecture Map: 12 Companies Sorted by Three Bottlenecks — 推理芯片架构地图：12 家公司按三大瓶颈分类
- Silicon Photonics Architecture: Quantifying Link Budgets and Optical Nonidealities — 硅光架构：链路预算与光非理想性的量化
- Lasers for CPO/NPO: Part 2 – Lumentum's Technology and Moat — CPO/NPO 激光器（二）：Lumentum 的技术与护城河
- Optics Primer, Part 3: Co-Packaged Optics (CPO) — 共封装光学 CPO 入门：从 EML/DSP 到硅光与外部 CW 激光
- The Illusion of CPO [CPO Special Final] — CPO 的幻象：方向人人都懂，坐标才分高下
- Lasers for CPO/NPO: Part 1 – The InP DFB Laser — CPO/NPO 激光器（一）：InP DFB 激光器原理
- The Open-Source AI Era: Will Hyperscalers Keep Buying Chips? — 开源 AI 时代：云巨头还会继续买芯片吗？
- TSMC Is Ahead in CPO. Samsung Is Putting a Third Chip Next to HBM — 台积电 CPO 领先，三星把第三颗芯片贴到 HBM 旁
- The Bandgap Reference: A Primer — 带隙基准源入门：PTAT/CTAT 抵消、Brokaw 结构与温度无关的基准电压
- Pushing the Speed Limit: Designing SerDes Transceivers for the 224 and 448Gbps Scaling Era — 突破速率极限：面向 224/448Gbps 时代的 SerDes 收发器系统架构拆解
- The Phase-Locked Loop: A Primer — 锁相环入门：从系统架构到 Type I/II PLL 的直观理解
- Signal Integrity: A Primer — 信号完整性入门：通道损耗、抖动与 SerDes 架构的第一性原理
- A Comprehensive Overview of High-Speed Optical Communications — 高速光通信全景：从 IM-DD、VCSEL 到硅光与相干光学
- Damnang's Optical Investment Map v1.0 — 光投资全产业链地图：7 层价值链与 50 只标的
- The 100-Second Bottleneck Behind NVIDIA CPO — CPO 测试瓶颈与四阶段测试栈
- Why You Should Be Watching Optical Test Right Now — 光测试赛道的投资逻辑与五大瓶颈